One byte shifting in transmit data in STM32F072RB while using SPI with DMA

[Sudharshan]

Hi Team,

Recently while working with STM32F072RB , I am using DMA mechanism with SPI. I am receiving a 63 bytes of data continuously from an external system at every 1ms.

In  STM32F072RB, I have enabled two SPI-SPI1 &SPI2. From/to the external system. I have to receive and transmit 63bytes of data simultaneously . I am receiving 63bytes of data in SPI1 and SPI2 happening with no shifting. 

But coming to the transmit part for SPI1 and SPI2, I am getting 63 bytes of data(i.e. frame 1 ), but in byte shifting is happening in this 63 bytes. For example , frame 1's last byte(62nd index position) is coming as 1st byte in the Frame2(0th index position)(checked in logic analyser) .

I am using below function for both SPI's.

HAL_SPI_TransmitReceive_DMA(&hspi2, (uint8_t*) aTxLeftBuffer,

(uint8_t*) aRxLeftBuffer, 63);

[TDK]

How could the last byte be from the next transaction? The chip time travels?

Perhaps show a complete example that exhibits the problem. The HAL_SPI_TransmitReceive_DMA function works, you can step through it and see what it does, or load example programs that use it.

[Sudharshan]

Hi Guru,

Thank you for your response.

The CS pin time is 1 millisecond, during which I need to transmit and receive data from two SPI devices simultaneously.

The problem I'm facing is a one-byte shift: the last byte of the first frame data is appearing as the first byte in the next frame. Additionally, some frames are being missed, resulting in data being received in alternate frames.

Here's the logic I'm using:

while (1) {
while (HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_4) == GPIO_PIN_RESET); // CS pin for SPI1
while (HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_4) == GPIO_PIN_SET);

SPI1_Communication();

while (HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_12) == GPIO_PIN_RESET); // CS pin for SPI2
while (HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_12) == GPIO_PIN_SET);

SPI2_Communication();
}

static void SPI1_Communication(void) {
// SPI1 communication
// HAL_SPI_Receive_DMA(&hspi1, (uint8_t*) aRxspi1Buffer, 63);
// HAL_SPI_Transmit_DMA(&hspi1, (uint8_t*) aTxspi1Buffer, 63);
HAL_SPI_TransmitReceive_DMA(&hspi1, (uint8_t*) aTxspi1Buffer, (uint8_t*) aRxspi1Buffer, 63);
}

static void SPI2_Communication(void) {
// SPI2 communication
HAL_SPI_TransmitReceive_DMA(&hspi2, (uint8_t*) aTxspi2Buffer, (uint8_t*) aRxspi2Buffer, 63);
// HAL_SPI_Receive_DMA(&hspi2, (uint8_t*) aRxspi2Buffer, 63);
// HAL_SPI_Transmit_DMA(&hspi2, (uint8_t*) aTxspi2Buffer, 63);
}

Previously, I had issues with receive data byte shifting, which were resolved using this logic. However, I'm still facing problems with the transmit data.

Here's the function I'm using to clear the RX FIFO:

void Clear_RXFIFO(SPI_HandleTypeDef *hspi) {
// Disable the SPI peripheral
__HAL_SPI_DISABLE(hspi);

// Read from the data register until the RXNE flag is reset
while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) {
uint8_t dummy = hspi->Instance->DR;
(void) dummy;
}

// Re-enable the SPI peripheral
__HAL_SPI_ENABLE(hspi);
}

I kindly request suggestions and corrections to help me fix this issue.

[TDK]

I suspect it's an issue with the CS line. Can you show the issue on a logic analyzer?

I see no code which manipulates CS, just code which waits for it to be toggled. How are those pins changing state?

[Sudharshan]

Hi Guru,

Thank you for your response. 

Sorry for late reply.

I am herewith attaching the snap shot of logic analyzer (for SPI 1). Similar for SPI2. 

The CS pin is active low .

[TDK]

Apart from MISO, everything looks fine to the extent that I can see. Can't resolve detail around CS edges.

If CS/SCK/MOSI signal are correct, nothing is wrong on the master/STM32 side.

What external device are you interfacing with? Are you meeting all of its specifications for data transfer?

[Sudharshan]

Hi Guru,

In our application STM32 is SPI slave mode, Above is reference block diagram, attached above is SPI-1 and SPI-2 waveforms in previous chat

Kindly guide as on Data transfer From Slave to master (MISO)

We are getting alternate frame miss in MISO as you can see in above waveform snaps in previous chain

As you mentioned CS/SCK/MOSI signal are correct, nothing is wrong on the master side -----> yes

We are facing issue in slave (STM32F072) data transfer to Master device

Quick solutions preferred. Kindly reply asap

If you need to have short call also, we are ready to explain the issues

[TDK]

I think it's a program logic issue. You're starting SPI1 transfer when SPI1_CS is low. Surely that's too late. The slave needs to be ready prior to the start of the transaction. Typically, one would resynchronize/queue the data on the CS rising edge.

Should also be monitoring for HAL return functions. My guess is you're not getting HAL_OK in all cases.

[Sudharshan]

Hi Guru,

Refer  below  for the CS pin status:

.During SPI Data Transfer Process,

1. Chip Select (CS) Pin Low: When the SPI Chip Select (CS) pin goes low, here it indicates that a data transfer operation is happening .

2.Data Transfer Initiation: As soon as the CS pin goes low, data transfer is initiated. The STM32 will first receive 63 bytes of data ,will be stored in the RX buffer and then transmit data . CS pin time is 1 millisecond, during which receive and transmit data to/from STM32 happen simultaneously.

3.Buffer Handling: After data transfer, the received 63 bytes of data will be stored in the RX buffer (aRxspi1Buffer).

But, when the SPI CS pin goes low- SPI 1 communication starts, Does receive happens first or transmit? Which happens initially based on HAL_SPI_TransmitReceive_DMA function ? Kindly guide me through . 

Kindly reply asap

Thanks