2023-08-02 11:48 PM - edited 2024-01-11 05:48 AM
STM32L4P5-DK has 5 external interrupt EXTI0 to EXTI4. Also vector address of all NVIC are given in the user manual. when I see the data stored in the vector address (say 0x0000 0060 for EXTI2) all the NVIC address have same data (i.e.,0xAD230008). May I know why all the data stored in different address are same?
Solved! Go to Solution.
2023-08-04 01:18 AM - edited 2023-08-04 01:21 AM
The lowest bit set indicates that the branch target address has thumb mode instructions. Always set for that Cortex-M core, ignore.
For details see
March 2020 PM0214 Rev 10 1/262
PM0214
Programming manual
STM32 Cortex® -M4 MCUs and MPUs programming manual
hth
KnarfB
2023-08-03 01:08 AM - edited 2023-08-03 01:11 AM
The table of all interrupt vectors g_pfnVectors is defined in the startup code startup_stm32l4*.s. Although each handler has a different name in that table like EXTI0_IRQHandler, most have the same default dummy implementation, the Default_Handler.
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
Only if you use an interrupt, say by activating EXTI1 in STM32CubeMX, a specific handler is generated in stm32l4xx_it.c which overrides the default (weak) handler. In addition, HAL often uses the same code for different instances of a peripheral and branches internally.
You see the address of the Default_Handler in all unused interrupt vector slots.
hth
KnarfB
2023-08-03 01:38 AM
> ,0xAD230008
The value should be read as 0x080023AD. And the address is 080023AC (guess why?)
2023-08-04 12:56 AM
why is that so..data+1= address?
2023-08-04 01:18 AM - edited 2023-08-04 01:21 AM
The lowest bit set indicates that the branch target address has thumb mode instructions. Always set for that Cortex-M core, ignore.
For details see
March 2020 PM0214 Rev 10 1/262
PM0214
Programming manual
STM32 Cortex® -M4 MCUs and MPUs programming manual
hth
KnarfB