Is it possible to have functional USB (with USBCLK 48Mhz) and optimal ADC (with APB2 14Mhz per the manual) simultaneously on the STM32F103C8? I've been using the clock tool in the IDE and every permutation I've tried either gives me one or the other.

DMill.16 · ‎2023-02-03

STOne-32 · ‎2023-02-04

Dear @DMill.16 ,

Here is the system clock tree of STM32F103C8, you can see that to have USB , system clock after PLL should be either 48MHz or 72MHz , then ADC Clock is coming from APB2 clock tree with divider ( 2, 4, 6 and 8). So let's assume you select 72MHz to get benefit from Maximum computing MIPs, ADC maximum Clock sampling will be 12MHz in that case which is the optimal ADC configuration.

If 14MHz is wanted from ADC, it is not possible to have USB and maximum system clock should be multiple of x14MHz, just as 56MHz. Hope it helps you.

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STOne-32 · ‎2023-02-04

Dear @DMill.16 ,

Here is the system clock tree of STM32F103C8, you can see that to have USB , system clock after PLL should be either 48MHz or 72MHz , then ADC Clock is coming from APB2 clock tree with divider ( 2, 4, 6 and 8). So let's assume you select 72MHz to get benefit from Maximum computing MIPs, ADC maximum Clock sampling will be 12MHz in that case which is the optimal ADC configuration.

If 14MHz is wanted from ADC, it is not possible to have USB and maximum system clock should be multiple of x14MHz, just as 56MHz. Hope it helps you.

DMill.16 · ‎2023-02-04

Thank you for answering.

Thank you for a complete answer - that expands on the question and clarifies the answer for future reference.

So this confirms what I found - with this particular processor I can have USB with suboptimal (probably good enough) ADC, or I can have optimal ADC without USB.