Will displays with approx. 720x1280 require only 2 lane DSI?

[Amelie ACKERMANN]

Is it correct to say that ST anticipates most displays with approx. 720x1280 will require only 2 lane DSI?

[Tesla DeLorean]

The question is awkwardly stated, but yes this around the ceiling for the megapixel counts at 16 bit colour depth at the 1Gbps of the two combined lanes.

The math is not exactly hard to do.

Basically the pixel clock out of the LTDC by the colour depth, with a little margin.

To get to FHD you need 4 lanes, and generally more capable hardware.

[Roman LUDIN]

On microcontrollers the targeted maximum recommended display definition is more 1024x600 16-bits to avoid compromise on the GUI content (amount of animation, slow screen transition, etc.). 1280x720x16-bits may indeed fit on 2 lanes but keep in mind that while a frame buffer is being transferred at 60Hz from external memory to the display through the DSI (LTDC running underneath), the next frame should also be prepared in parallel, maybe in a second frame buffer, this is where the memory bandwidth can become a bottleneck. Please have a look at the following application note for further details; https://www.st.com/resource/en/application_note/an4861-lcdtft-display-controller-ltdc-on-stm32-mcus-stmicroelectronics.pdf