STM32MP1 using FMC from CM4 core

[MCarl.3]

We are using the STM32MP15 ecosystem 2.1.0 and buildroot build flow for a custom board.  The custom board uses the FMC peripheral to connect to three FPGAs using an SRAM/PSRAM interface.  We have successfully implemented this interface on the CA7 side by writing a custom kernel driver, but would now like to move this function to the CM4.   After using CubeMX to move the peripheral to the CM4, there is an error in the generated device tree for the kernel, specifically there is a missing symbol “m4_fmc�? in the generated device tree.

I looked at the STMicro kernel repos on GitHub at the in-tree stm32mp157-m4-srm.dtsi file for both ecosystem 2.1.0(v5.4-stm32mp1-r2.1) and 3.0.0 (v5.10-stm32mp1-r1) and there is no definition for “m4_fmc�? in either version.

Does this mean that the FMC for the STM32MP15x is not yet supported by HAL? Or just an oversight?

Thanks,

Mark Carlin

[MCarl.3]

For anyone out there that is trying to use the FMC from the CM4 core, you need to patch the stm32mp157-m4r-srm.dtsi device tree file in the kernel and u-boot to add the following to the &m4_rproc node.

        m4_fmc: memory-controller@58002000 {
            compatible = "rproc-srm-dev";
            reg = <0x5800200 0x1000>;
            clocks = <&rcc FMC_K>;
            clock-names = "mux";
            status = "disabled";
        };

STM32CubeIDE actually does generate some ll code for the FMC, you can modify this easily for SRAM/NOR use, but there are no drivers for NAND.

Cheers,

Mark

[ArnaudP]

Hello @Community member​ 

First of all, thanks you for taking the time to share the Solution!

Indeed adding this node prevents that the Linux disables the FMC parent clock. More details available here:

https://wiki.st.com/stm32mpu-v3.0.0/wiki/How_to_configure_system_resources

In addition I suppose that you have also enabled the node in your dts, right?

 &m4_fmc {
	status = "okay";
 };

[MCarl.3]

Hi @ArnaudP​ ,

Yes, the kernel dts must have the node enabled as you indicated. We can now configure FPGA, read/write and get interrupts from three FPGAs.