Hi,
I have enabled iwdg2 in tf-a, uboot (PV="v2023.10-stm32mp-r1") , optee (version 4.0.0-stm32mp) and linux kernel(ver. v6.6-stm32mp) device trees for STM32MP133F. iwdg is enabled in non-secure world only.
&iwdg2 {
status = "okay";
/* USER CODE BEGIN iwdg2 */
timeout-sec = <60>;
/* USER CODE END iwdg2 */
};
When stopping in u-boot there are 2 scenarios that manifest as watchdog caused reset.
1. First scenario is when the system is just stopped and inactive in u-boot.
2. Second scenario is when running mtest in u-boot. (mtest writes and reads to addresses from 0xc0000000 to 0xc4000000; excluding the end address)
With op-tee watchdog reset there is Panic stack unwind:
E/TC:0 Panic 'Watchdog' at /usr/src/debug/optee-os-stm32mp/4.0.0-stm32mp-r1/core/drivers/stm32_iwdg.c:228 <stm32_iwdg_it_handler>
E/TC:0 TEE load address @ 0xce000000
E/TC:0 Call stack:
E/TC:0 0xce00a1d4 print_kernel_stack at /usr/src/debug/optee-os-stm32mp/4.0.0-stm32mp-r1/core/arch/arm/kernel/unwind_arm32.c:109
E/TC:0 0xce086f08 __do_panic at /usr/src/debug/optee-os-stm32mp/4.0.0-stm32mp-r1/core/kernel/panic.c:88
E/TC:0 0xce03902c stm32_iwdg_it_handler at /usr/src/debug/optee-os-stm32mp/4.0.0-stm32mp-r1/core/drivers/stm32_iwdg.c:228
E/TC:0 0xce0821ac interrupt_call_handlers at /usr/src/debug/optee-os-stm32mp/4.0.0-stm32mp-r1/core/kernel/interrupt.c:91
E/TC:0 0xce02e8d0 gic_native_itr_handler at /usr/src/debug/optee-os-stm32mp/4.0.0-stm32mp-r1/core/drivers/gic.c:659
E/TC:0 0xce02e900 interrupt_main_handler at /usr/src/debug/optee-os-stm32mp/4.0.0-stm32mp-r1/core/drivers/gic.c:670
E/TC:0 0xce000388 vector_fiq_entry at tmp-glibc/work/mcm_ng-oe-linux-gnueabi/optee-os-stm32mp/4.0.0-stm32mp-r1/git/core/arch/arm/kernel/thread_optee_smc_a32.S:93
And this is another example of watchdog reboot where the system is stopped in u-boot (debug traces are enabled with additional watchdog reset debug trace added).
16:54:45:688 -> stm32mp-wdt watchdog@5a002000: IWDG reset
16:54:46:688 -> stm32mp-wdt watchdog@5a002000: IWDG reset
16:54:47:688 -> stm32mp-wdt watchdog@5a002000: IWDG reset
16:54:48:688 -> stm32mp-wdt watchdog@5a002000: IWDG reset
...
...
17:19:47:718 -> stm32mp-wdt watchdog@5a002000: IWDG reset
17:19:48:718 -> stm32mp-wdt watchdog@5a002000: IWDG reset
17:21:16:953 -> NOTICE: CPU: STM32MP133F Rev.Y
17:21:16:956 -> NOTICE: Model: STMicroelectronics custom STM32CubeMX board - openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06
17:21:16:978 -> NOTICE: Reset reason (0x204):
17:21:16:981 -> INFO: IWDG2 Reset (rst_iwdg2)
After some time the u-boot stops refreshing watchdog and there is subsequent reset.
Can you please suggest how to debug this issue and if there is something wrong with described iwdg2 configuration?
