STM32MP1 DDR3L Fly-By Topology without Write/Read Leveling

[SYEH]

Hi There,

I have a question regarding with DDR3L fly-by topology suggested to use by the design guide.

My understanding is that STM32MP1 does not support the write/read leveling feature suggested in the JESD standard.

If my above understanding is correct, may I ask then why fly-by topology is still recommended as opposite to the T-topology?

I thought the main reason DDR3/DDR3L uses fly-by topology is because the write/read leveling feature allows the controller to compensate the skew between CK/DQS caused by the daisy chain connection from fly-by topology.

I have also seen other vendor's hardware development manual (i.e. NXP iMX7) that specifically recommend not to use fly-by topology, as their chip does not support write/read leveling feature.

Am I missing something here? or perhaps my understanding is incorrect?

Appreciate your assistance in advance.

Thanks.

Regards,

Steven

[mleo · Accepted solution]

Hi @SYEH​ ,

Yes, STM32MP1 does not support write/read leveling, these feature are NOT essential at 533MHz (DDR-1066) 

Fly-by connection is recommended instead of T connection in case of dual DDR3 device for better Signal Integrity and easier PCB routing.

AN5122 explicit the layout guidelines and constraints (lane matching .etc) compatible with this approach for DDR-1066MHz

Best regards,

Milan