About SYEH

SYEH · 2020-08-09

Hi There,I have a question regarding with DDR3L fly-by topology suggested to use by the design guide.My understanding is that STM32MP1 does not support the write/read leveling feature suggested in the JESD standard.If my above understanding is correc...

SYEH · 2020-03-03

Hi There,When the STPMIC1 goes into POWER_ON ALTERNATE mode via the PWRCTRL pin, does the activation of other Turn-ON condition sources like PONKEY or WAKEUP pins will have a resulting effect to the state of POWER_ON mode? (i.e. also triggers the PMI...

SYEH · 2019-11-21

For STPMIC1, when it is powered on by asserting the PONKEYn signal low, what would happen if the PONKEYn remains asserted low even after the initial POWER_ON trigger? Would it subsequently trigger a POWER_DOWN if PONKEYn long press turn off is activa...

SYEH · 2020-03-11

Thanks on the answers. All clear now. Cheers.

SYEH · 2020-03-03

Thanks the prompt reply,Understood. May I confirm with you on the "poweroff" command behaviour when used on the STM32MP157C-EV1 evaluation board? As I find it quite confusing when trying to map it to with STMIC1 state machine, especially I can actual...

SYEH · 2019-12-02

Hi Olivier,Thanks for the response. Much appreciated. All clear now.Cheers.Steven

SYEH · 2019-11-26

Hi Olivier,Thanks for the reply. Understood.Is that the same for the WAKEUP pin? As in the WAKEUP POWER_ON event will only trigger from LOW to HIGH edge transition, and does not require to stay HIGH after the initial trigger?Thanks.Steven.

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STM32MP1 DDR3L Fly-By Topology without Write/Read Leveling

STPMIC1 - POWER_ON ALTERNATE & MAIN mode

STPMIC1 - PONKEYn POWER_ON POWER_DOWN trigger

Re: STPMIC1 - POWER_ON ALTERNATE & MAIN mode

Re: STPMIC1 - POWER_ON ALTERNATE & MAIN mode

Re: STPMIC1 - PONKEYn POWER_ON POWER_DOWN trigger

Re: STPMIC1 - PONKEYn POWER_ON POWER_DOWN trigger