RMGII Routing guidelines for STM32MP151XXX

[DMårt]

Hi!

Are there any RMGII routing guidelines for the STM32MP151XXX series that are available for use?

I have a Realtek RTL8211F-CG Ethernet PHY and I don't know how long the RX and TX lines should be.

[PatrickF]

HI @DMårt 

Did you have a look to AN5031 ?

with RGMII, as clock and associated data are in same direction, you could probably achieve easily 10-15cm wire length if you do careful PCB.

You should route TX and RX part (data+associated clock) altogether, 50 ohms with balanced length (+/- few mm).

Avoid via and connectors when possible (i.e. to keep impedance as constant as possible within the transmission lines).

Careful compute microstip impedance with your real PCB stackup and have reference power plane juste below signals (classic pitfall).

If wires are 'long' (lets says more than 3cm), it is strongly recommended to put 22 ohms serie resistor close to each driver side to avoid too much reflection.

You could get reference design by looking at STM32MP157F-DK2 which use RTL8211F (https://www.st.com/en/evaluation-tools/stm32mp157f-dk2.html#cad-resources)

Notice that even if working, long lines are not good for EMI.

Regards.

[DMårt]

1. OK. So if I got short lines, about 10-15 cm...Well, I have max 2 cm as length

2. OK. Same length for all RX and TX lines and they all should have 50 ohm microstip impedance as well.

3. OK. Avoid via connection as much as possible

4. OK. Have a long distance between the signals and power plane.

5. In my case, the TX lines are short. Max 2 cm. The RX lines are longer.

6. According to AN5031, the differential lines should be 100 ohm impedance as well.

[PatrickF · Accepted solution]

Hi,

point 4 is not true. You must have power plane below as this is the reference for microstip impedance calculation. This is usual duty for people doing high-speed PCB. Your PCB is likely having 4 or 6 layers. Please refer to examples (e.g. gerber PDF in en.mb1272-manufacturing.zip)

For point 6. There is no differential line on RGMII side. For the Ethernet connector side, please refer to Ethernet PHY documentation and PCB guidelines.

Regards.

[DMårt]

So all signal lines should be at the top layer and below the signal lines, the laywer below, it should be the 3.3V plane?

Signal layer 2 is very close to top-layer.