NETDEV WATCHDOG: eth0 (cpsw): transmit queue 0 timed out

[Wjian.1]

Hi：

​Anyone familiar with this issue?When I plug in the network cable, the following information will be printed later:

[ 373.607360] ------------[ cut here ]------------

[ 373.610551] WARNING: CPU: 1 PID: 0 at net/sched/sch_generic.c:447 dev_watchdog+0x300/0x304

[ 373.618870] NETDEV WATCHDOG: eth0 (stm32-dwmac): transmit queue 0 timed out

[ 373.625765] Modules linked in: aes_arm_bs crypto_simd cryptd algif_skcipher brcmfmac cfg80211 galcore(OE) hci_uart brcmutil btbcm stm32_cec spi_stm32 sch_fq_codel ipv6 nf_defrag_ipv6

[ 373.642115] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G          OE    5.4.31 #1

[ 373.649368] Hardware name: STM32 (Device Tree Support)

[ 373.654536] [<c01124dc>] (unwind_backtrace) from [<c010d784>] (show_stack+0x10/0x14)

[ 373.662275] [<c010d784>] (show_stack) from [<c0bead54>] (dump_stack+0xb0/0xc4)

[ 373.669510] [<c0bead54>] (dump_stack) from [<c0125b24>] (__warn+0xd0/0xf8)

[ 373.676384] [<c0125b24>] (__warn) from [<c0125f00>] (warn_slowpath_fmt+0x98/0xc4)

[ 373.683872] [<c0125f00>] (warn_slowpath_fmt) from [<c0a9eac4>] (dev_watchdog+0x300/0x304)

[ 373.692063] [<c0a9eac4>] (dev_watchdog) from [<c019ca4c>] (call_timer_fn+0x3c/0x20c)

[ 373.699812] [<c019ca4c>] (call_timer_fn) from [<c019d1ec>] (run_timer_softirq+0x218/0x5d0)

[ 373.708087] [<c019d1ec>] (run_timer_softirq) from [<c01022f0>] (__do_softirq+0x148/0x43c)

[ 373.716276] [<c01022f0>] (__do_softirq) from [<c012ca8c>] (irq_exit+0xc8/0xe0)

[ 373.723504] [<c012ca8c>] (irq_exit) from [<c017a4b4>] (__handle_domain_irq+0x80/0xe8)

[ 373.731350] [<c017a4b4>] (__handle_domain_irq) from [<c05e2a58>] (gic_handle_irq+0x4c/0x90)

[ 373.739705] [<c05e2a58>] (gic_handle_irq) from [<c0101a8c>] (__irq_svc+0x6c/0xa8)

[ 373.747182] Exception stack(0xdf0c5f80 to 0xdf0c5fc8)

[ 373.752241] 5f80: 00000000 00050fcc dfaf5074 c011b740 00000001 df0c4000 c1204ea8 c1204ee8

[ 373.760428] 5fa0: c000406a 410fc075 00000000 00000000 00000000 df0c5fd0 c010a1a4 c010a1a8

[ 373.768606] 5fc0: 60010013 ffffffff

[ 373.772101] [<c0101a8c>] (__irq_svc) from [<c010a1a8>] (arch_cpu_idle+0x38/0x3c)

[ 373.779503] [<c010a1a8>] (arch_cpu_idle) from [<c0158404>] (do_idle+0xc4/0x14c)

[ 373.786817] [<c0158404>] (do_idle) from [<c0158778>] (cpu_startup_entry+0x18/0x20)

[ 373.794394] [<c0158778>] (cpu_startup_entry) from [<c010268c>] (__enable_mmu+0x0/0x14)

[ 373.802389] ---[ end trace 6e1a18e6e110c983 ]---

Thanks & Regards

[AgaGioUmpiSrl]

I have a similar problem when I start the firmware on the M4 core ...

[ 224.064973] ------------[ cut here ]------------

[ 224.068178] WARNING: CPU: 0 PID: 0 at net/sched/sch_generic.c:466 dev_watchdog+0x248/0x24c

[ 224.076364] NETDEV WATCHDOG: eth0 (stm32-dwmac): transmit queue 0 timed out

[ 224.083267] Modules linked in: brcmfmac galcore(O) cfg80211 brcmutil

[ 224.089592] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G      O   4.19.94 #1

[ 224.096932] Hardware name: STM32 (Device Tree Support)

[ 224.102069] [<c031269c>] (unwind_backtrace) from [<c030cd3c>] (show_stack+0x10/0x14)

[ 224.109753] [<c030cd3c>] (show_stack) from [<c0ee542c>] (dump_stack+0xb0/0xc4)

[ 224.116934] [<c0ee542c>] (dump_stack) from [<c0347130>] (__warn.part.3+0xbc/0xd8)

[ 224.124370] [<c0347130>] (__warn.part.3) from [<c03471b4>] (warn_slowpath_fmt+0x68/0x8c)

[ 224.132415] [<c03471b4>] (warn_slowpath_fmt) from [<c0db0370>] (dev_watchdog+0x248/0x24c)

[ 224.140552] [<c0db0370>] (dev_watchdog) from [<c03b9508>] (call_timer_fn+0x3c/0x200)

[ 224.148249] [<c03b9508>] (call_timer_fn) from [<c03b98d8>] (expire_timers+0xb4/0x15c)

[ 224.156034] [<c03b98d8>] (expire_timers) from [<c03b9cc4>] (run_timer_softirq+0xac/0x1ac)

[ 224.164168] [<c03b9cc4>] (run_timer_softirq) from [<c0302274>] (__do_softirq+0x14c/0x420)

[ 224.172303] [<c0302274>] (__do_softirq) from [<c034d4c0>] (irq_exit+0xc8/0xdc)

[ 224.179482] [<c034d4c0>] (irq_exit) from [<c039ad44>] (__handle_domain_irq+0x80/0xec)

[ 224.187271] [<c039ad44>] (__handle_domain_irq) from [<c069e528>] (gic_handle_irq+0x58/0x9c)

[ 224.195573] [<c069e528>] (gic_handle_irq) from [<c0301a0c>] (__irq_svc+0x6c/0xa8)

[ 224.203004] Exception stack(0xc1801f10 to 0xc1801f58)

[ 224.208027] 1f00:                   00000000 00026bb0 dbb7d54c c031e220

[ 224.216162] 1f20: ffffe000 c1804c78 c1804cbc 00000001 c1804c48 00000000 c175e628 c13ddc1c

[ 224.224292] 1f40: c1804d58 c1801f60 c0309384 c0309388 60030013 ffffffff

[ 224.230873] [<c0301a0c>] (__irq_svc) from [<c0309388>] (arch_cpu_idle+0x38/0x3c)

[ 224.238228] [<c0309388>] (arch_cpu_idle) from [<c0375904>] (do_idle+0x1dc/0x288)

[ 224.245577] [<c0375904>] (do_idle) from [<c0375c88>] (cpu_startup_entry+0x18/0x1c)

[ 224.253105] [<c0375c88>] (cpu_startup_entry) from [<c1600e20>] (start_kernel+0x45c/0x48c)

[ 224.261256] ---[ end trace a68fd34659c8be43 ]---

[ 224.265882] stm32-dwmac 5800a000.ethernet eth0: Reset adapter.

[ 224.375456] SMSC LAN8710/LAN8720 stmmac-0:00: attached PHY driver [SMSC LAN8710/LAN8720] (mii_bus:phy_addr=stmmac-0:00, irq=POLL)

[ 225.388528] stm32-dwmac 5800a000.ethernet: Failed to reset the dma

[ 225.393248] stm32-dwmac 5800a000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed

[ 225.402822] stm32-dwmac 5800a000.ethernet eth0: stmmac_open: Hw setup failed

... after that I no longer have the network.

[AgaGioUmpiSrl]

Look here https://wiki.st.com/stm32mpu/wiki/Ethernet_overview (5.3 How to debug↑)

and here https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration

[PatrickF]

I confirm that usually error like "Failed to reset the dma" on ETH IP is related to IP does not receive all expected clocks. You should check which https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration is matching your system design.

For detail on ETH clocking, please refer to RCC section in RM0436, look at "Clock distribution for Ethernet (ETH)".

Regards

[ap-swapp]

ETH clock stops because of incorrect use of SET_BIT macro on rc_w1 registers.

For example this is the case when HAL_SYSCFG_AnalogSwitchConfig() is called.

void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
 {
   /* Check the parameter */
   assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
   assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
   SET_BIT(SYSCFG->PMCCLRR, SYSCFG_AnalogSwitch);
   SET_BIT(SYSCFG->PMCSETR, (uint32_t)(SYSCFG_SwitchState));
 }

The macro SET_BIT is defined as follows:

#define SET_BIT(REG, BIT)     ((REG) |= (BIT))

SET_BIT at line 6 of HAL_SYSCFG_AnalogSwitchConfig() function will reset any bit read at logic level 1 (and possibly bits related to ETH clocks that are housed on the same register).

The correct way to manage rc_w1 registers is to write directly the mask containing bits that must be cleared.

The same is true for rs registers.

In the above axample lines 6 and 7 should be:

SYSCFG->PMCCLRR = SYSCFG_AnalogSwitch;
SYSCFG->PMCSETR = (uint32_t)(SYSCFG_SwitchState);

Please note that STM32Cube_FW massively uses SET_BIT macro...

I'm afraid that other registers are wrongly managed in such a way.

Regards.

[AgaGioUmpiSrl]

This solves my problem!

[AgaGioUmpiSrl]

This solves my problem!