Failed to access ROM Table of CortexM4 while debugging in engineering mode. What are the reasons ? See description below.

WSief.1 · ‎2023-05-15

Product: STM32MP153CAA3

we are trying to debug the Cortex M4 over the SWD Interface. The setup of the Bank0,1,2 is configured correct (Engineering Mode) . During the analysis of SWD we see that Debugger fails to access ROM Table (Address: 0xE00FFFE4, CM4ROM_PIDR1) Expected alue is 0x004. Read value is 0x7310F507

The IDCODE and the settings of registers before are matching the expectation.

What are the reasons for failing to access those registers ? (clocks, voltage ...)

Tesla DeLorean · ‎2023-05-15

Power (Low Power modes?)

Contention (Uses same bus as MCU to read the memory content)

Locked/Protection (Things that might actively limit you access to resources and functionality)

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WSief.1 · ‎2023-05-16

To the topic before:

Can MPU enter Low Power Mode in Engineering Boot mode?

PatrickF · ‎2023-05-17

Hi @WSief.1 ,

maybe your debugger does not use the right DAP acces-port.

This ROM table is visible on AHB-AP access-port (AP2) dedicated to Cortex-M4 (and not accessible from AXI-AP (AP0) AXI interconnect as at those addresses there is the DDR).

Tested with Lauterbach Trace32 connected on Cortex-M4, using SWD on a STM32MP157F-EV1 board in Engineering mode (aka Development boot) without any specific settings.

Maybe you could tell your debugger to avoid using ROM table based automated discovery and instead use your debugger 'manual' setup for STM32MP153C which is usually available.

Regards.

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