About DDR Bitswapping

[tatsuya]

Hi

Currently, I'm designing a PCB with "STM32MP151AAD3T".

I'm developing our own PCB with reference to "STM32MP157x-EV1".

DDR trace wiring is described in Section 3.2 of "AN5122" as follows:

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Point-to-point connection of the data bus (2 swappable bytes, and swappable bits in the same byte):

– 16 data signal bits (DQ)

– 2 data mask signals (DQMx)

– 2 differential clocks (DQSx_N/DQSx_P)

********************************************************************************​

What kind of criteria should I apply to swap bits(DQ) in the same byte?

Can I prioritize pattern routing?

Best regards,

[info]

swap the data bits and byte lanes to suit the routing. Only the address lines are relevant during initialization and of course operation of the DRAM. The bits do not matter - but any swap must remain inside it's own byte lane (do not swap bits across lanes)

[PatrickF · Accepted solution]

Hi @tatsuya​ ,

I confirm the @info​ statements. The swapping allows routing optimization (avoid vias, stubs, optimize lengths, etc...).

For your own PCB, unless you are expert on DDR routing, we recommend to stick (or reuse as much as possible) the routing examples provided together with AN5122 (STM32MP1 Series DDR memory routing guidelines examples).

Note that when using 16-bits DDR3/DDR3L on a device supporting 32-bits, only DQ0-DQ15 should be used (i.e. only swap byte0 with byte1 is possible, byte2 and byte3 are left open).

Note also that unlike DDR3/DDR3L, for LPDDR2/LPDDR3, the byte0 must never be swapped (neither byte nor bits) as byte0 is used for memory mode register control.

Regards.

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[tatsuya]

Patrick-san

Thank you for useful informations.

> For your own PCB, unless you are expert on DDR routing, we recommend to stick (or reuse as much as possible) the routing examples provided together with AN5122 (STM32MP1 Series DDR memory routing guidelines examples).

Since I'm a beginner for DDR3L, so I'll refer to the following materials. (single DDR3L mounted)

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STM32MP1_SeriesDDRmemory_routing_guidelines_layout_examples_V3.0\STM32MP15XXAD\STM32MP15XXAD_1DDR3L\Schematics\STM32MP15XXAD_1DDR3Lx16-Example-B01_Schematic.PDF

*********************************************************

Can I ask about implementation of DDR3L as follows.

Q1. Should I place the "damping resistors(33ohm)" shown in "STM32MP15XXAD_1DDR3Lx16-Example-B01_Schematic.PDF"?

Should these "damping resistors" be placed close to the output pins of STM32MP151?

Q2. In case of configuring my system with "single DDR3L", is it correct that the terminating resistors is not necessary?

In the example of "STM32MP15XXAD_1DDR3Lx16-Example-B01_Schematic.PDF", the circuit is composed with one DDR3L, so the termination resistors are not implemented.

Best regards,

[info]

I have done just that recently - just use the same track layout as in the sample. No damping resistors. Works great. Did not even have to tune it - drop in and go !

[PatrickF]

I confirm the @info​ statement. If you use a single x16 DDR3L device and you route it short and respecting AN5122 (or simpler, copying a provided example), neither damping nor terminations resistors are needed. There is multiple SOM maker examples using this way to build very small solutions.

We found out that DDR3L timings at 533MHz with STM32MP15 are quite robust and usually fly with default settings from CubeMx.

Regards.

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