SPI in slave mode transfers data till it has data to send on master clocks

[tachyontechnologies]

Hi, I have an application where the SPI master is sending data every 2 mSecs. The STM32MP157F-DK

2 SPI4 and SPI5 are in slave mode. They are receiving the data as expected but the data is skipped between each transfer on SPI4 and SPI5. The application to read the data from master is a threaded application in user space.

The data received on SPI4 between 2 subsequent transfers skips 40 to 50 millisecond of data since I have data every 2 mSecs each second there would be 500 packets of close to 80 bytes. From my experiments I have come to know the data is read from the Master only when we have data to send.

Attached is the sample data which is showing the observations as above.

I would like to change the behavior in a way that SPI4 and SPI5 are always active or can read data without a huge gap between subsequent transactions.
Can you please guide what changes or configuration may work here?

Note: the original requirement to read the data without any subsequent transaction failure is at 200uSecs.

[DBELL.1]

Hello @tachyontechnologies ,

Did you try to configure the SPIs with DMA?
This could free some CPU bandwidth.

rgds,
David B

[tachyontechnologies]

Hi, thank you for replying on this thread. I have the configuration for DMA enabled in the device tree but there is no framework to read the raw data in dma mode it seems. My requirement is to read a continuous stream from master from application point of view I am not sure if DMA can be configured from User space. Please guide me if you have any context on this it would be very much helpful.