sgtl5000 codec dsi i2c

Ara.1 · ‎2021-08-06

Hi All,

i am using stm32mp1 with i2c on sgtl5000 codec and control lines are over carrier i2s

i am getting kernel soc sgtl5000.c error

sgtl5000 0-000a: Error reading chip id -6

<STM32_PINMUX('A', 15, AF5)>; /* I2S1_WS */

<STM32_PINMUX('Z', 0, AF5)>, /* I2S1_CK */

<STM32_PINMUX('Z', 1, AF5)>, /* I2S1_SDI */

<STM32_PINMUX('Z', 2, AF5)>, /* I2S1_SDO */

<STM32_PINMUX('Z', 6, AF5)>; /* I2S1_MCK */

Any reference dts on i2s1 would be helpful.. and suggest on kernel error .

Bernard PUEL · ‎2021-09-02

With your devicetree mclk should be there and looking to the codec code, you can see there is no error to get the mclk before the error on the chip ID.

So the idea was the delay to enable the clock between the 2 blocs (only one usec) was not enough ... udelay(1000) may be tried.

Then the next idea would be to activate the dynamic traces into the i2s driver to see what happens.

Then next possibility would be a pb of clock management due to 4.19 kernel + Mclk backport. Between 4.19 and 5.10, scmi was enabled to manage the clocks.

I will review with experts and let you know.

Ara.1 · ‎2021-09-02

Yes Please, thanks please do review with expert and let m know

i never seen mclk after the configure stm32_i2s_configure is getting called /stm32-i2s start which does after root login prompt, i believe the same behavior exist in 5.10.XX , as we don't have sgtl5000 external crystal connect 24 mclk , we totally depends on SOC/SOM i2s_mclk, to detect SGTL5000 on i2c, by default to make it ON on stm32_i2s_probe

Ara.1 · ‎2021-09-02

i believe the mclk also not enabled in 5.10.xx, as the codecs are fed with crystal frequency, which codec active by default, but there are some board design like us who depends on internal mclk generation, MCLK is not live until codec sub stream is ready

Ara.1 · ‎2021-09-02

i believe the mclk also not enabled in 5.10.xx, as the codecs are fed with crystal frequency, which codec active by default, but there are some board design like us who depends on internal mclk generation, MCLK is not live until codec sub stream is ready

Ara.1 · ‎2021-09-03

Hi Bernard,

1, i have tried udelay(1000) i2c detect fail

2.any direct patch/ which file to be concern ?

would be a pb of clock management due to 4.19 kernel + Mclk backport. Between 4.19 and 5.10, scmi was enabled to manage the clocks.

3, is there any patch possible to generate always i2s mclk enable and generate contious clk in stm32_i2s_probe ?, this i would prefer fix, but depends on experts call.

Bernard PUEL · ‎2021-09-03

Hello,

Just reviewed deeply the use case with experts. Many things to share.

First to answer your questions:

We do think 5.10 / 4.19 is not a pb. With your backport there should not be any pb.
To force the mclk: there is no magic commands and the ones done in the codec drivers are the only ones (clk_get + clk_prepare_enable)

Few remarks:

in your latest dts, i understand your i2s node is in i2c nodes (maybe i am wrong). Please make sure it is like below:

&i2c {

sgtl5000 {

clocks = <&i2s1>;

…

};

&i2s1 {

#clock-cells = <0>;

mclk-fs = <256> ;

…

}

There is suspicion the clock got from the dts is not the right one here: "sgtl5000->mclk = devm_clk_get(&client->dev, NULL);" . Could you replace this code to explicitly name this clock "sgtl5000->mclk = devm_clk_get(&client->dev, "mclk");" ? Check there is no error.
after the probing of the codec (that fails), could you please print clock tree: "Board $> cat /sys/kernel/debug/clk/clk_summary" ?
Activating the i2s dynamic debug, you can check the master clock is enabled or not in the i2s driver (there is a dbg print)

I hope this will give some information about what happens.

On any other kernel clock, we can force them to be always active but here with the I2S, this is dependent from the activation of the I2S peripheral.

Ara.1 · ‎2021-09-04

Hi Bernard,

I have made

dts change

&i2c {

sgtl5000 {

clocks = <&i2s1>;

…

};

kernel/driver

sgtl5000,c change as "mclk", still i didnt get mclk during probe of SGTL, but i see mclk is getting after 35 sec, where the root login prompt comes, which

you can see sgtl5000 lies at 0x0a, but probe still fails which means that i2s block is not providing the mclk during sgtl5000 probe,

if you have demo probe may you confirm the behaviour, but i see in scope after 35sec gets mclk enabled, following is the log

[ 34.016482] sound/soc/stm/stm32_i2s.c stm32_i2s_startup:953

[ 34.020706] sound/soc/generic/audio-graph-card.c asoc_graph_card_startup::75 ret 0

[ 34.028307] sound/soc/generic/audio-graph-card.c asoc_graph_card_startup::80 ret 0

[ 34.036399] sound/soc/generic/audio-graph-card.c asoc_graph_card_hw_params::110 ret 0

[ 34.043703] sound/soc/generic/audio-graph-card.c asoc_graph_card_hw_params::120 ret mclk 11289600

[ 34.052714] sound/soc/soc-core.c snd_soc_dai_set_sysclk 2499 dai->driver->ops->set_sysclk 0

[ 34.061041] sound/soc/soc-core.c snd_soc_component_set_sysclk 2525 ************************8 11289600 0

[ 34.078598] sound/soc/soc-core.c snd_soc_dai_set_sysclk 2499 dai->driver->ops->set_sysclk c08ca710

[ 34.086125] sound/soc/stm/stm32_i2s.c stm32_i2s_set_sysclk:663 cpu_dai 44004000.audio-controller (null)

[ 34.098170] ****************I2S MCLK frequency is 11289600Hz. mode: master, dir: output

[ 34.104740] sound/soc/stm/stm32_i2s.c stm32_i2s_set_sysclk:673 freq 11289600 dir 1 mode 1

[ 34.113210] sound/soc/stm/stm32_i2s.c stm32_i2s_set_sysclk:695

[ 34.119263] sound/soc/stm/stm32_i2s.c stm32_i2s_set_sysclk:714

[ 34.126283] sound/soc/stm/stm32_i2s.c stm32_i2s_set_sysclk:719-- enable_mclk 5

[ 34.132270] sound/soc/stm/stm32_i2s.c stm32_i2s_set_sysclk:729-- enable_mclk 5

[ 34.140539] sound/soc/stm/stm32_i2s.c stm32_i2s_set_sysclk:737

[ 34.145158] sound/soc/stm/stm32_i2s.c stm32_i2s_set_sysclk:738 mck oe

the above does not come during sgtl probe,

if you have demo board may you confirm the behavior ?

Bernard PUEL · ‎2021-09-06

Do you see some probe differ in the log before this kernel trace ?

Bernard PUEL · ‎2021-09-06

could you please share the part of the log where the sgtl5000 driver is probed ?

Ara.1 · ‎2021-09-06

[ 4.419496] sgtl5000 0-000a: enabling clock 0

[ 4.424913] sgtl5000 0-000a: Error reading chip id -6