I would like to connect the FMC interface to external 12bit, 80MHz ADC. 1. Does the STM32MP151 support such rate? 2. How should I configure the bus?

[PatrickF]

Hello,

please precise if you plan to use this with Cortex-A7 (Linux) or Cortex-M4.

FMC is not really tailored for such usage, as I assume you want to have continuous data provided by the ADC at 80MHz rate.

FMC is intended to read data from SRAM-like device in asynchornous or synchronous way, but sound not possible to read such rate.

For Cortex-M4 side, maybe possible to use DCMI for such usage, but 80MHz is still at the edge about IP capabilities. And I' not sure ADC could connect directly.

[Estei.1]

Hi Patrick,
OK. Thanks.
What about regular GPIOs? Will they be able to be read as a bus in such rate? For example PortA[15:0]/PortB[15:0] etc?
Eyal

[PatrickF]

Hi,

GPIO input cannot be read at 80MHz. The APB bus is at 104.5MHz max and there is a need of few clock cycles to read one data (not including the time for a master such as a DMA to process it and store in memory).

Btw, which processing do you plan to have in SW on this 1Gbit/s of data (160MBytes/s assuming 2 bytes to store one 12-bit sample) ?

I fear you have to pre-process your data externally (e.g. FPGA connected on FMC, which could filter or else and drastically reduce data rate managed by the System).

Maybe have a look to QUADSPI which could read data in DDR mode at 80MHz clock. You need to be clever and have some external logic to drive 8bits on one edge and 4 bits on another one (or 6+6 if easier). But as SPI is not a continuous input, you need also external Fifo somewhere.

[Estei.1]

Hi,
What about the DCMI? Can this port be used?
Eyal

[PatrickF]

DCMI could theoretically be used up to 80MHz, but as it is intended for image, there is always some blanking period without pixels. This periods are used to re-arm the DMA in between frames (and on Linux, this could be quite constraining).

In your case, I understood you want continuous stream of analog sample, which is quite different than image pixels.

You could have a try using DCMI/DMA managed by Cortex-M4. I will not guarantee that it will work without tricky configuration and SW.

Probably need to use SRAM intermediate buffer rather than directly DDR.

Issue might be also to transfer these data from SRAM to DDR (and Linux) in a right way (see https://wiki.st.com/stm32mpu/wiki/How_to_exchange_large_data_buffers_with_the_coprocessor_-_principle). 160MBytes/s mean exchanging a 32KBytes buffer every 200us.