GPIO port documentation query: P-MOS is shown inverted but is active high, and vice versa for N-MOS

[tarmasr]

With reference to RM0436, the STM32MP157 Reference Manual, revision 6.

On pages 1066 and 1072 the schematic structures of a GPIO port are drawn (figures 119, 120, and 122). These all show an inverter circle on the gate of P-MOS output transistor and none on the N-MOS transistor. This suggests that the P-MOS is active low and the N-MOS is active high.

However, the written documentation states the opposite: that the P-MOS is active high (pulls the output pin high for a "1" bit unless in open-drain mode) and the the N-MOS is active low (pulls the output pin low for a "0" bit).

From experience I believe that the written documentation is correct, so should the schematic not be redrawn to show the inverter circle on the gate of the N-MOS output transistor?

Attached please find annoted screen shots of the pages in question.

[PatrickF · Accepted solution]

Hi @tarmasr ,

the 'bubble' present on the P-MOS gate is more a drawing convention to distinguish a P-MOS from an N-MOS than a real implemented logic inverter.

The text in the reference manual does not details how the 'output control' box work from output data register (yes, there should likely be an inverted somewhere in it), but rather to explain the push-pull or open-drain behavior (where in the open-drain case, the P-MOS is never activated).

I would not take drawings in the GPIO sections as an exact description of the implementation, but rather some help to understand the different part involved in each modes.

Regards.

[tarmasr]

Thanks @PatrickF 

Understood; I stand corrected. I am used to arrows to indicate the P-ness or N-ness of transistors, but you are right: in the absence of arrows a small circle on the gate designates the P-MOS.