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Error in debugging cortex M4 core in engineering mode of STM32MP157C-DK2 board.

SNand.2
Associate

‎2021-07-11 11:30 PM

I am using PlatformIO extension on Visual Studio Code and ZephyrRTOS framework to run blinky sample code for stm32mp157c-dk2 board in engineering mode. my use-case is to debug only in engineering mode with A7 core not being active or running.

Debugging in engineering mode is not getting started and "target needs reset " message(line-39) is thrown in debug terminal as shown below

undefinedC:\Users\E0565260\.platformio\packages\toolchain-gccarmnoneeabi\bin\arm-none-eabi-gdb.exe: warning: Couldn't determine a path for the index cache directory.
 
Reading symbols from C:\Users\E0565260\Documents\PlatformIO\Projects\test4_mp1\.pio\build\disco_mp157c_dk2\firmware.elf...
PlatformIO Unified Debugger -> http://bit.ly/pio-debug
PlatformIO: debug_tool = stlink
PlatformIO: Initializing remote target...
xPack OpenOCD, x86_64 Open On-Chip Debugger 0.11.0-00155-ge392e485e (2021-03-15-16:44)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
srst_only srst_pulls_trst srst_gates_jtag srst_open_drain connect_deassert_srst
 
Info : tcl server disabled
Info : telnet server disabled
Info : STLINK V2J32M22 (API v2) VID:PID 0483:3752
Info : Target voltage: 3.192142
2
Info : Unable to match requested speed 5000 kHz, using 4000 kHz
Info : clock speed 4000 kHz
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x6ba02477
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x6ba02477
Info : stm32mp15x.cm4: hardware has 6 breakpoints, 4 watchpoints
Info : stm32mp15x.cpu0: hardware has 6 breakpoints, 4 watchpoints
Info : stm32mp15x.cpu0 rev 5, partnum c07, arch f, variant 0, implementor 41
Info : stm32mp15x.cpu0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT
Info : stm32mp15x.cpu1: hardware has 6 breakpoints, 4 watchpoints
Info : stm32mp15x.cpu1 rev 5, partnum c07, arch f, variant 0, implementor 41
Info : stm32mp15x.cpu1: MPIDR level2 0, cluster 0, core 1, multi core, no SMT
Info : starting gdb server for stm32mp15x.cpu0 on pipe
Info : starting gdb server for stm32mp15x.cm4 on pipe
Info : accepting 'gdb' connection from pipe
Info : New GDB Connection: 1, Target stm32mp15x.cpu0, state: halted
Info : accepting 'gdb' connection from pipe
Info : New GDB Connection: 2, Target stm32mp15x.cm4, state: halted
4
Error: GDB missing ack(2) - assumed good
undefined debug reason 8 - target needs reset
8
Error: GDB missing ack(2) - assumed good
SystemInit () at C:\Users\E0565260\.platformio\packages\framework-zephyr-hal-stm32\stm32cube\stm32mp1xx\soc\system_stm32mp1xx.c:149
149	  CLEAR_REG(EXTI_C2->IMR3);
2
Error: GDB missing ack(2) - assumed good
23
Warn : negative reply, retrying
Ignoring packet error, continuing...
3
Warn : negative reply, retrying
Ignoring packet error, continuing...
3
Warn : negative reply, retrying
Ignoring packet error, continuing...
Warn : negative reply, retrying
.pioinit:14: Error in sourced command file:
Reply contains invalid hex digit 6
 
 

Exploring the cofig file stm32mp15x.cfg in target folder of OpenOCD i can see (line 43-52) some reset for M4 core related issue is there which might be blocking my debug run.

# STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4)
# http://www.st.com/stm32mp1
 
# HLA does not support multi-cores nor custom CSW nor AP other than 0
if { [using_hla] } {
	echo "ERROR: HLA transport cannot work with this target."
	echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp15x_dk2.cfg\"."
	shutdown
}
 
source [find target/swj-dp.tcl]
 
if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME stm32mp15x
}
 
if { [info exists CPUTAPID] } {
	set _CPUTAPID $CPUTAPID
} else {
	if { [using_jtag] } {
		set _CPUTAPID 0x6ba00477
	} else {
		set _CPUTAPID 0x6ba02477
	}
}
 
# Chip Level TAP Controller, only in jtag mode
if { [info exists CLCTAPID] } {
	set _CLCTAPID $CLCTAPID
} else {
	set _CLCTAPID 0x06500041
}
 
swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
if { [using_jtag] } {
	jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
}
 
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
 
# FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1
# so defer-examine it until the reset framework get merged
# NOTE: keep ap-num and dbgbase to speed-up examine after reset
# NOTE: do not change the order of target create
target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000
target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
 
targets $_CHIPNAME.cpu0
 
target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
$_CHIPNAME.cpu0 cortex_a maskisr on
$_CHIPNAME.cpu1 cortex_a maskisr on
$_CHIPNAME.cpu0 cortex_a dacrfixup on
$_CHIPNAME.cpu1 cortex_a dacrfixup on
 
cti create $_CHIPNAME.cti.sys  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0094000
cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D8000
cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D9000
cti create $_CHIPNAME.cti.cm4  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE0043000
 
swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0083000
tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0093000
 
# interface does not work while srst is asserted
# this is target specific, valid for every board
# Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires
# srst to force VDDCORE power cycle or pull srst_core. Both cases reset the
# debug unit, behavior equivalent to "srst_pulls_trst"
reset_config srst_gates_jtag srst_pulls_trst
 
adapter speed 5000
adapter srst pulse_width 200
# bootrom has an internal timeout of 1 second for detecting the boot flash.
# wait at least 1 second to guarantee we are out of bootrom
adapter srst delay 1100
 
add_help_text axi_secure "Set secure mode for following AXI accesses"
proc axi_secure {} {
	$::_CHIPNAME.dap apsel 0
	$::_CHIPNAME.dap apcsw 0x10006000
}
 
add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
proc axi_nsecure {} {
	$::_CHIPNAME.dap apsel 0
	$::_CHIPNAME.dap apcsw 0x30006000
}
 
axi_secure
 
proc dbgmcu_enable_debug {} {
	# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
}
 
proc toggle_cpu0_dbg_claim0 {} {
	# toggle CPU0 DBG_CLAIM[0]
	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
}
 
proc detect_cpu1 {} {
	$::_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1
	set dual_core [expr {$cpu1_prsr(0) & 1}]
	if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
}
 
proc rcc_enable_traceclk {} {
	$::_CHIPNAME.ap2 mww 0x5000080c 0x301
}
 
# FIXME: most of handler below will be removed once reset framework get merged
$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;dap init;catch {$::_CHIPNAME.dap apid 1}}
$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
$_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
$_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
$_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
$_CHIPNAME.ap1  configure -event examine-start       {dap init}
$_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}
$_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}
$_CHIPNAME.ap2  configure -event examine-end         {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}

Can anyone suggest how to have a work around for this particular issue?

thanks and regards

Sumit

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3 REPLIES 3
Olivier GALLIEN
ST Employee

‎2021-07-12 01:30 AM

Hi @SNand.2​ ,

Thanks for your post.

Actually I'm not aware of this platformIO extension for Visual Studio code configuration.

Is it this extension which bring the STM32MP1 support ?

Which version of OpenOCD are you using and where did you get it ?

Did you make a try to use STM32CubeIDE solution ?

That would give some reference for OpenOCD working scripts.

Hope it help

Olivier

Olivier GALLIEN
In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.
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SNand.2
Associate

‎2021-07-12 03:05 AM

Hi, @Community member​  Thanks for your response.

Can you point me to any references(wiki page or User Mannuals) for debugging in the engineering mode of STM32MP157 DK2 board with STM32CubeIDE? I tried browsing for same but all i could find was references to use A7 core to boot M4.

PlatformIO brings the support for multiple boards on VS Code but STM32MP157C-DK2 is not one of them yet. I am using PlatformIO as my other projects on F4, F7, H7 controllers are already working on PlatformIO and my team is keen on having the same IDE. PlatformIO uses OpenOCD in background when debug is started. It uses version 0.11 of OpenOCD

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skuma.9
Associate II

‎2022-10-19 02:52 AM

Hi @SNand.2​ ,

I am working ZephyrRTOS framework and want to make setup for debugging for target stm32mp157c-dk2 board in engineering mode. Want to debug ARM Cortex-M4 Core of the STM32MP1 Devices in engineering mode.

I found that openocd not supported for cortex-M4 target.

Could u suggest How u find the solution for this.

If opened can un suggest how to proceed with this.

Thanks!!

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