WB55: Leaving the chip in the brick after loading the stack. Very important for everyone.

[Vyacheslav]

2 years ago it happened that the controller turned to brick. I corresponded with technical support for a long time and I was offered to send the controller to the factory or representative. But since the case was a single one, I did not take advantage of this case and forgot about it.

Now there is a situation that, probably, everyone who uses this chip has, namely, that for unknown reasons it turns into a brick.

I re-read all my messages in the STM community, but to my surprise, the post in which I described the transformation into brick disappeared.

Today I have about 70 controllers with which I cannot do anything because they are not programmable.

I decided to understand the reason and found it.

The reason is well described in the post:

https://community.st.com/s/feed/0D53W000010si7oSAA?t=1676280731376

But for all this time, not a single STM employee has given a clear explanation of why this is happening.

The question is simple: why sometimes, after loading the stack, the chip register SFSA = 0?

After all, because of this, the chip turns into a brick.

I lost some money to buy the chips, but I lost a lot more because I couldn't sell my final product.

How long will STM keep silent about this problem?

None of the ERRATAs describe this case.

It turns out that STM does not give a damn about its consumers?

If the official representatives do not answer this question, I will raise a storm on the Internet about the quality of the chips and the sabotage of employees in front of consumers.

Vyacheslav : Bluetooth SIG Id is "LVI Cо."

[Peter BENSCH]

Is it possible that this is your old thread?

Please keep in mind, that the community is a place for questions where users can benefit from the experiences of other users. Now that @Remi QUINTIN​ has helped you before, perhaps he will be so kind again?

Regards

/Peter

[Vyacheslav]

Thanks for the quick response.

But this is not the thread.

By the way, the problem was not solved in the specified thread either, so we still use the version of SDK 1.11 in the old device only because of the indicated problem.

And the thread about which I spoke, where the states of the register were indicated many times - it does not exist.

 

[RByli.1]

I have the same problem. During the erasure of all memory, sometimes the chip turns into a brick. Through st link, you can only read the memory. It is impossible to change anything. Sometimes this happens when the stack is loaded. Indeed the ship register SFS A = 0

I have a lot of such chips. I don't know what to do with them now.

Best regards

TheRom

[Remy ISSALYS]

Hello,

Can you share the value of SBRV option byte? And which FUS version did you used?

Best Regards

[Vyacheslav]

Hello, Remy.

The default FUS in clear chip is 1.2.0

   -------------------------------------------------------------------

            STM32CubeProgrammer v2.12.0          

   -------------------------------------------------------------------

ST-LINK SN : 53FF6A064975524934100567

ST-LINK FW : V2J36S7

Board    : --

Voltage   : 3.22V

SWD freq  : 4000 KHz

Connect mode: Normal

Reset mode : Software reset

Device ID  : 0x495

Revision ID : Rev Y

Device name : STM32WB5x/35xx

Flash size : 1 MBytes

Device type : MCU

Device CPU : Cortex-M4

BL Version : 0xD5

Debug in Low Power mode enabled

UPLOADING OPTION BYTES DATA ...

 Bank     : 0x00

 Address    : 0x58004020

 Size     : 96 Bytes

±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±± 0%

џџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ 100%±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±±± 50%

џџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ 100%

 Bank     : 0x01

 Address    : 0x58004080

 Size     : 8 Bytes

OPTION BYTES BANK: 0

  Read Out Protection:

   RDP     : 0xAA (Level 0, no protection) 

  BOR Level:

   BOR_LEV   : 0x0 (BOR Level 0 reset level threshold is around 1.7 V) 

  User Configuration:

   nBOOT0    : 0x1 (nBOOT0=1 Boot from main Flash) 

   nBOOT1    : 0x1 (Boot from code area if BOOT0=0 otherwise system Flash) 

   nSWBOOT0   : 0x1 (BOOT0 taken from PH3/BOOT0 pin) 

   SRAM2RST   : 0x0 (SRAM2 erased when a system reset occurs) 

   SRAM2PE   : 0x1 (SRAM2 parity check disable) 

   nRST_STOP  : 0x1 (No reset generated when entering the Stop mode) 

   nRST_STDBY  : 0x1 (No reset generated when entering the Standby mode) 

   nRSTSHDW   : 0x1 (No reset generated when entering the Shutdown mode) 

   WWDGSW    : 0x1 (Software window watchdog) 

   IWDGSTDBY  : 0x1 (Independent watchdog counter running in Standby mode) 

   IWDGSTOP   : 0x1 (Independent watchdog counter running in Stop mode) 

   IWDGSW    : 0x1 (Software independent watchdog) 

   IPCCDBA   : 0x0 (0x0) 

  Security Configuration Option bytes - 1:

   ESE     : 0x1 (Security enabled) 

  PCROP Protection:

   PCROP1A_STRT : 0x1FF (0x80FF800) 

   PCROP1A_END : 0x0 (0x8000800) 

   PCROP_RDP  : 0x1 (PCROP zone is erased when RDP is decreased) 

   PCROP1B_STRT : 0x1FF (0x80FF800) 

   PCROP1B_END : 0x0 (0x8000800) 

  Write Protection:

   WRP1A_STRT  : 0xFF (0x80FF000) 

   WRP1A_END  : 0x0 (0x8000000) 

   WRP1B_STRT  : 0xFF (0x80FF000) 

   WRP1B_END  : 0x0 (0x8000000) 

OPTION BYTES BANK: 1

  Security Configuration Option bytes - 2:

   SFSA     : 0x0 (0x8000000) 

   FSD     : 0x0 (System and Flash secure) 

   DDS     : 0x1 (CPU2 debug access disabled) 

   C2OPT    : 0x1 (SBRV will address Flash) 

   NBRSD    : 0x0 (SRAM2b is secure) 

   SNBRSA    : 0x0 (0x20038000) 

   BRSD     : 0x0 (SRAM2a is secure) 

   SBRSA    : 0x0 (0x20030000) 

   SBRV     : 0x3FC00 (0x20000000) 

Regards,

Vyacheslav.

[Vyacheslav · Accepted solution]

I solved my problem.

Thanks to the topic

https://community.st.com/s/question/0D53W00000fnOhSSAU/wireless-stack-recovery-for-stm32wb?t=1676621574060

Now I can restore chips.

The procedure is as follows:

Using STM32CubeProgrammer via ST-Link.

- "User Configuration" option bytes bring it to the factory initial state.

- write 0x00008000 to the PWR_CR4 register. (start CPU2)

-wait 5 seconds after which the remaining registers of options bytes dependent on CPU2 return to safe boot state.

- hard reset chip.

Now chip in factory default state.

But it works only if FUS V1.1.0 or higher version.

If a FUS version lower than V1.1.0 is running, then, no recovery is possible at this point. (AN5185 page 10)

Regards,

Vyacheslav.