STM32WL55 High power TX @ 1.8V

[Albi G.]

Hi,

i am working within a 1.8V system for digital supply. I am currently designing the schematic but I struggle how to integrate the STM32WL55 into an 1.8V system while assuring I am able to achieve +22dBm output power. The issue is that the datasheets says one MUST connect VDDRF and VDDSMPS to VDD thus limiting the radio power supply to the 1.8V of the digital domain.

With only 1.8V the maximum transmit power is only +16dBm which cuts the transmit distance by 1/4.

I cannot change VDD to anything else than 1.8V as other lower power components rely on it.

Is there any workaround for this limitation?
For example is it possible to connect a 3V supply to VDDPA in order to supply the PA-Regulator with a separate power supply?
Or could I just supply my own power via a tunable supply voltage to RFO_HP (basically substituting the PA-Regulator with my own external circuit).

I am struggling with this limitation in a big way. Especially this limitation contradicts the low power claims, and example circuits that are floating around (MB1789_HP) actually split VDD and VDDRF which makes no sense within the context of the datasheet.

Can anyone explain why this limitation (VDDRF == VDD) exists in the first place? Is this due to EDS protection??

[Albi G.]

I still need help / detail on this.

If it is hard to confirm possible workarounds, can someone give me information about the PA topology? Is it Class-E, Class-A with inductive biasing or is it class-D?

In case of class A or E the idea to supply external power via the biasing inductor could work if
a) PA-Output pin pin has a high enough voltage tolerance
b) the gate-drive of the output stage uses a static voltage that does not depend on the output power.

It would also help to know which voltage-range the internal PA-regulator covers - just as a starting point.

[STTwo-32]

Hello @Albi G. 

When working in 1.8V The VDDRF must be connected to the same supply as VDD. So, we can have a Transmit output power of 16 dBm maximum. 

Best Regards.

STTwo-32

[Albi G.]

Thank you.

Lets say loosing 6dB tx-power due to 1.8V IO constraint is unacceptable, could I bias the PA with an external voltage up to 3.0V?

[Rob555]

I have the same question. Can I run the i/o at 1.8V, but the PA at 3.0V ?

A bit more on this from my perspective.
With reference to the Nucleo-WL5JC schematics, device U3 enables VDDPA to be sourced from either VDDRF1V5 (default Tx power) or VDD_RF (high Tx power).
Would it therefore be ok to run VDDRF and VDDSMPS at 3.3V for high power but run VDD, VDDA and Vref+ at 1.8V for 1.8V i/o ?