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Radio frequency communication between Nucleo-WL55jc2 and radio frequency Device

Zayoud
Associate II

Hi ST experts.

I used the pingpong sample code with the tutorial I have found in the TechForum: Link of the tutorial in order to establish the radio frequency communication between two Nucleo-WL55JC2 boards and it works. 

establishing RF communication 2 Nucleo-wl.png

 And then I tried to communicate with the device that has this configuration 

Zayoud_0-1708436178652.png

It didn't work with my code, I searched for the problem and I found on the configuration of the subghz: 

cube mx config .png

What is the role of the baudrate prescaler value for the subghz configuration?

and what changes should I make?

1 ACCEPTED SOLUTION

Accepted Solutions
STTwo-32
ST Employee

Hello @Zayoud  and welcome to the ST Community 😊.

According to the RM0453, The sub-GHz radio SPI clock is derived from the PCLK3 clock. The SUBGHZSPI_SCK
frequency is obtained by PCLK3 divided by two. The SUBGHZSPI_SCK clock maximum
speed must not exceed 16 MHz. So, the  baudrate prescaler value should be 4 or more in case PCLK3 clock is 48MHz or 2 in case PCLK3 clock is 32MHz. 

STTwo32_0-1708540054989.png

So, the baudrate prescaler value is the frequency divider value. it set exactly the 3 bits of the Baud rate control on the SUBGHZSPI_CR1:

STTwo32_2-1708540250567.pngSTTwo32_3-1708540271607.png

Best regards.

Liltek Zina.

STTwo-32

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

View solution in original post

2 REPLIES 2
Andrew Neil
Evangelist

@Zayoud  wrote:

I used the pingpong sample code with the tutorial I have found in the TechForum: Link of the tutorial 


That's DigiKey's forum - nothing to do with ST.

https://forum.digikey.com/t/using-the-low-level-sub-ghz-radio-driver-for-the-stm32wl-series/18253/11 

As it says there, they're throwing away ST's standard code, and doing something "different" instead - so you'd probably be better asking the actual author there what it is that he's done, and how to understand & use his code!

 


@Zayoud  wrote:

What is the role of the baudrate prescaler value for the subghz configuration?


AndrewNeil_1-1708442134506.png

 

 

STTwo-32
ST Employee

Hello @Zayoud  and welcome to the ST Community 😊.

According to the RM0453, The sub-GHz radio SPI clock is derived from the PCLK3 clock. The SUBGHZSPI_SCK
frequency is obtained by PCLK3 divided by two. The SUBGHZSPI_SCK clock maximum
speed must not exceed 16 MHz. So, the  baudrate prescaler value should be 4 or more in case PCLK3 clock is 48MHz or 2 in case PCLK3 clock is 32MHz. 

STTwo32_0-1708540054989.png

So, the baudrate prescaler value is the frequency divider value. it set exactly the 3 bits of the Baud rate control on the SUBGHZSPI_CR1:

STTwo32_2-1708540250567.pngSTTwo32_3-1708540271607.png

Best regards.

Liltek Zina.

STTwo-32

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.