STM32H7 slave mode timing issue above 22.8 MHz

[Amit_RS]

Hello all,

This is regarding the the problem after recent development from 18MHz to 22.8 MHz of operational speed of STM as slave operating with DMA transfer and SPI mode 01. Although the data sheet suggest maximum achievable speed of 31 MHz - I made it up to 22.8 MHz, beyond which data corruption occurs. As per my recent findings there is a persistent lag between the SCK and MISO signal around 8.8 -10.4 ns. I tested the SPI communication with and without hardware NSS, also with only SPI communication shutting of other operations but this delay is still there. Please find the oscilloscope readings for the reference.
tsu (NSS)tv(SO)tw(SCKH)th(SO)

In oscilloscope readings GREEN is NSS (CS), BLUE is SCK(Clock) and YELLOW is MISO signal.

Further checking into the data sheet I found the following information:

Comparing the oscilloscope readings with the data sheet information it feels like this lag (tv(SO)) is hardware limitation and can't be decreased. And at higher frequency this delay takes maximum of the clock signal duration thus giving a bit shift of 1 digit i.e 00111101 00010111 is recorded as 00011110 10001011, which corrupts the data received.
Is there any possible way to make it work at 31 MHz. I am using SPI5 with DMA as slave. Also 2 max speeds are mentioned for slave mode in the table - which I don't get, is it for any specific SPI or what does it mean?
Thanking you all.

[JBias]

Since the ST is the slave the timing specification Tv(SO) is fixed as you found observed. Worst case is 16nsec, which should be the criteria used when designing for the master device. You are reading a typical of 8-10nsec which starts to fail at the 22MHz range but I would design for the possibility of 16nsec.

So what I would like to see is what the master device timing looks like to be able to tell what max frequency between these two devices can be. It takes two to communicate and while the ST can push 31MHz as slave, if the master can not operate with the Tv(SO) given then you are forced to operate at a lower speed.

Possibilities are to make changes to either the master or slave if needing the higher speeds.

The second question was about the two listings in the chart. The Vdd can be variable for I/O and if it is higher, above 2.7V,  you get a faster I/O as shown in the chart. Again the Vdd must be in spec for both the ST Slave and the master devices. Here's a spec:

You will have to check the schematic for what Vdd your setup is using.

[AScha.3]

Hi,

Just I didn't get it,

Can you specify, what you doing:

STM32 H7?? Is slave mode: receive or transmitter?

And timing looks ok, cool 0 and cpha 1 .

If that's what you set.

And who is master then?

[Amit_RS]

The STM is full duplex SPI slave while CM pi 4 is master. But right now the focus is more on STM to transmit properly to the master.

[AScha.3]

Did you try with cpol 0 and cpha 0 ?

[MasterT]

Regarding two max speed, 

• Slave mode transmitter/full
  duplex
  2.7 V≤VDD≤3.6 V           31
  Slave mode transmitter/full
  duplex
  1.62 V≤VDD≤3.6 V         25

Last line should be 1.62 V≤VDD≤2.7 V.   Lower voltage range, lower speed, logically. Strange things, already DS Rev.9 and nobody notices.

I had an issue with bit shifting in one of my project on H743zi2 , spi in slave mode with baudrate >30 MHz, than I switched  spi to TI_Mode. Try.

[JBias]

So you are doing high speed communications between cores with M7 (SPI5 slave, DMA) and M4 (SPI?, DMA) and you are not able to have the slave transmit correctly above 22.8MHz?

Have you set the SPI GPIO lines to Very High Speed?

[David Littell]

Your scope says your signals need some cleanup.  

How are the Master and Slave connected?  Good ground, signal-path length matching, and terminations become more important at these speeds.  You really can't just run fly leads and hope for the best.  Well, you can...

Have you looked for reflections on the clock and MISO signals?  Signal path routing and terminations can make a huge difference here too.