Hello all,
This is regarding the the problem after recent development from 18MHz to 22.8 MHz of operational speed of STM as slave operating with DMA transfer and SPI mode 01. Although the data sheet suggest maximum achievable speed of 31 MHz - I made it up to 22.8 MHz, beyond which data corruption occurs. As per my recent findings there is a persistent lag between the SCK and MISO signal around 8.8 -10.4 ns. I tested the SPI communication with and without hardware NSS, also with only SPI communication shutting of other operations but this delay is still there. Please find the oscilloscope readings for the reference.
In oscilloscope readings GREEN is NSS (CS), BLUE is SCK(Clock) and YELLOW is MISO signal.
Further checking into the data sheet I found the following information:
Comparing the oscilloscope readings with the data sheet information it feels like this lag (tv(SO)) is hardware limitation and can't be decreased. And at higher frequency this delay takes maximum of the clock signal duration thus giving a bit shift of 1 digit i.e 00111101 00010111 is recorded as 00011110 10001011, which corrupts the data received.
Is there any possible way to make it work at 31 MHz. I am using SPI5 with DMA as slave. Also 2 max speeds are mentioned for slave mode in the table - which I don't get, is it for any specific SPI or what does it mean?
Thanking you all.
