What Causes Artifacts in Displays Like the Following:

[Richard Lowe]

I'm getting the following artifacts in the display and as of today, haven't tracked down the cause. I've adjusted DSI clock timings, LTDC clock timings, and SRAM timings. Caching is configured as off for the SRAM via MPU. Any ideas?

[Osman SOYKURT]

Hello @Richard Lowe ,

It's definitely too slow. That's why I would suggest you to try to use a lower bpp format and see if it helps.
I think that there's maybe too much data to traffic between SDRAM and the MCU. The time needed for data transfer between SDRAM and MCU must be (much) lower than your vsync period in order to make the screen work properly.

[Osman SOYKURT]

Hello @Richard Lowe ,

Any updates concerning your issue?