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DSI LCD point and methods for call init display controller IC ... conc NV3051D pdf attached

MM..1
Chief II

‎2021-01-11 08:54 AM

I have issue with init LCD 480x1280 with this IC connected 2 lanes to STM32F469. When i init DSI host to video mode and after start DSI init display commands, display isnt synced properly. Help please. Image is horizontaly shifted . I test hundret combination porch and timing, nothing helps.

uint8_t lcdRegData[2];
 
extern DSI_HandleTypeDef    hdsi;
 
void Wrt_Reg_3052(uint8_t Par1,uint8_t Par2)
{
	lcdRegData[0]=Par2;
	HAL_DSI_LongWrite(&hdsi, 0, DSI_DCS_LONG_PKT_WRITE, 1, Par1, lcdRegData);
}
 
uint8_t NV3051D_Init(uint32_t ColorCoding, uint32_t orientation)
{
	LCD_RESET_GPIO_Port->BSRR = LCD_RESET_Pin;
	HAL_Delay(1);
	HAL_GPIO_WritePin(LCD_RESET_GPIO_Port, LCD_RESET_Pin, GPIO_PIN_RESET);
	HAL_Delay(1);
	LCD_RESET_GPIO_Port->BSRR = LCD_RESET_Pin;
 
	HAL_Delay(150);
	HAL_DSI_Start(&(hdsi));
	HAL_Delay(15);
 
	Wrt_Reg_3052(0xFF,0x30);
	Wrt_Reg_3052(0xFF,0x52);
	Wrt_Reg_3052(0xFF,0x01);
	Wrt_Reg_3052(0xE3,0x00);
	Wrt_Reg_3052(0xF6,0xC0);
	Wrt_Reg_3052(0xF0,0x00);
 
	Wrt_Reg_3052(0x24,0x08);
	Wrt_Reg_3052(0x25,0x0A);
 
	Wrt_Reg_3052(0x28,0x64);
	Wrt_Reg_3052(0x29,0xc4);
 
	Wrt_Reg_3052(0x38,0x74);
	Wrt_Reg_3052(0x39,0x7F);
	Wrt_Reg_3052(0x3A,0x53);//
 
	Wrt_Reg_3052(0x20,0x90);//2lane
 
 
	Wrt_Reg_3052(0x40,0x12);
	Wrt_Reg_3052(0x49,0x3C);
	Wrt_Reg_3052(0x6D,0x00);
	Wrt_Reg_3052(0x6E,0x00);
 
	Wrt_Reg_3052(0x91,0x77);
	Wrt_Reg_3052(0x92,0x77);
 
	Wrt_Reg_3052(0xA0,0x55);
	Wrt_Reg_3052(0xA1,0x50);
 
	Wrt_Reg_3052(0xA3,0xD8);
	Wrt_Reg_3052(0xA4,0x9C);
 
	Wrt_Reg_3052(0xA7,0x02);
	Wrt_Reg_3052(0xA8,0x01);
	Wrt_Reg_3052(0xA9,0x01);
	Wrt_Reg_3052(0xAA,0xA8);
	Wrt_Reg_3052(0xAB,0x28);
	Wrt_Reg_3052(0xAC,0xE0);
	Wrt_Reg_3052(0xAD,0xE2);
	Wrt_Reg_3052(0xAE,0xE2);
	Wrt_Reg_3052(0xAF,0x02);
	Wrt_Reg_3052(0xB0,0xE2);
	Wrt_Reg_3052(0xB1,0x26);
	Wrt_Reg_3052(0xB2,0x28);
	Wrt_Reg_3052(0xB3,0x28);
	Wrt_Reg_3052(0xB4,0x22);
	Wrt_Reg_3052(0xB5,0xE2);
	Wrt_Reg_3052(0xB6,0x26);
	Wrt_Reg_3052(0xB7,0xE2);
	Wrt_Reg_3052(0xB8,0x26);
 
	Wrt_Reg_3052(0xFF,0x30);
	Wrt_Reg_3052(0xFF,0x52);
	Wrt_Reg_3052(0xFF,0x02);
	Wrt_Reg_3052(0xB1,0x05);
	Wrt_Reg_3052(0xD1,0x05);
	Wrt_Reg_3052(0xB4,0x2C);
	Wrt_Reg_3052(0xD4,0x2A);
	Wrt_Reg_3052(0xB2,0x01);
	Wrt_Reg_3052(0xD2,0x01);
	Wrt_Reg_3052(0xB3,0x29);
	Wrt_Reg_3052(0xD3,0x27);
	Wrt_Reg_3052(0xB6,0x07);
	Wrt_Reg_3052(0xD6,0x05);
	Wrt_Reg_3052(0xB7,0x2C);
	Wrt_Reg_3052(0xD7,0x2A);
	Wrt_Reg_3052(0xC1,0x05);
	Wrt_Reg_3052(0xE1,0x05);
	Wrt_Reg_3052(0xB8,0x0A);
	Wrt_Reg_3052(0xD8,0x0A);
	Wrt_Reg_3052(0xB9,0x01);
	Wrt_Reg_3052(0xD9,0x01);
	Wrt_Reg_3052(0xBD,0x14);
	Wrt_Reg_3052(0xDD,0x14);
	Wrt_Reg_3052(0xBC,0x12);
	Wrt_Reg_3052(0xDC,0x12);
	Wrt_Reg_3052(0xBB,0x10);
	Wrt_Reg_3052(0xDB,0x10);
	Wrt_Reg_3052(0xBA,0x10);
	Wrt_Reg_3052(0xDA,0x10);
	Wrt_Reg_3052(0xBE,0x17);
	Wrt_Reg_3052(0xDE,0x19);
	Wrt_Reg_3052(0xBF,0x0E);
	Wrt_Reg_3052(0xDF,0x10);
	Wrt_Reg_3052(0xC0,0x17);
	Wrt_Reg_3052(0xE0,0x19);
	Wrt_Reg_3052(0xB5,0x37);
	Wrt_Reg_3052(0xD5,0x32);
	Wrt_Reg_3052(0xB0,0x02);
	Wrt_Reg_3052(0xD0,0x05);
 
	Wrt_Reg_3052(0xFF,0x30);
	Wrt_Reg_3052(0xFF,0x52);
	Wrt_Reg_3052(0xFF,0x03);
	Wrt_Reg_3052(0x00,0x00);
	Wrt_Reg_3052(0x01,0x00);
	Wrt_Reg_3052(0x02,0x00);
	Wrt_Reg_3052(0x03,0x00);
 
/*	Wrt_Reg_3052(0x08,0x8d);
	Wrt_Reg_3052(0x09,0x8c);
	Wrt_Reg_3052(0x0A,0x8b);
	Wrt_Reg_3052(0x0B,0x8a);
*/	Wrt_Reg_3052(0x08,0x8b);
	Wrt_Reg_3052(0x09,0x8a);
	Wrt_Reg_3052(0x0A,0x89);
	Wrt_Reg_3052(0x0B,0x88);
 
	Wrt_Reg_3052(0x30,0x00);
	Wrt_Reg_3052(0x31,0x00);
	Wrt_Reg_3052(0x32,0x00);
	Wrt_Reg_3052(0x33,0x00);
	Wrt_Reg_3052(0x34,0x81);
	Wrt_Reg_3052(0x35,0x26);
	Wrt_Reg_3052(0x36,0x66);
	Wrt_Reg_3052(0x37,0x13);
 
/*	Wrt_Reg_3052(0x40,0x8a);
	Wrt_Reg_3052(0x41,0x8b);
	Wrt_Reg_3052(0x42,0x88);
	Wrt_Reg_3052(0x43,0x89);
*/	Wrt_Reg_3052(0x40,0x8b);
	Wrt_Reg_3052(0x41,0x8a);
	Wrt_Reg_3052(0x42,0x89);
	Wrt_Reg_3052(0x43,0x88);
	Wrt_Reg_3052(0x45,0x00);
	Wrt_Reg_3052(0x46,0x01);
 
	Wrt_Reg_3052(0x48,0x02);
	Wrt_Reg_3052(0x49,0x03);
 
/*	Wrt_Reg_3052(0x50,0x86);
	Wrt_Reg_3052(0x51,0x87);
	Wrt_Reg_3052(0x52,0x84);
	Wrt_Reg_3052(0x53,0x85);
*/	Wrt_Reg_3052(0x50,0x87);
	Wrt_Reg_3052(0x51,0x86);
	Wrt_Reg_3052(0x52,0x85);
	Wrt_Reg_3052(0x53,0x84);
 
	Wrt_Reg_3052(0x55,0x04);
	Wrt_Reg_3052(0x56,0x05);
	Wrt_Reg_3052(0x58,0x06);
	Wrt_Reg_3052(0x59,0x07);
 
	Wrt_Reg_3052(0x80,0x0f);
	Wrt_Reg_3052(0x81,0x0f);
	Wrt_Reg_3052(0x82,0x0e);
	Wrt_Reg_3052(0x83,0x0f);
	Wrt_Reg_3052(0x84,0x04);
	Wrt_Reg_3052(0x85,0x05);
	Wrt_Reg_3052(0x86,0x06);
	Wrt_Reg_3052(0x87,0x07);
	Wrt_Reg_3052(0x88,0x0f);
	Wrt_Reg_3052(0x89,0x0e);
	Wrt_Reg_3052(0x8A,0x00);
	Wrt_Reg_3052(0x8B,0x01);
 
	Wrt_Reg_3052(0x96,0x0f);
	Wrt_Reg_3052(0x97,0x0f);
	Wrt_Reg_3052(0x98,0x0e);
	Wrt_Reg_3052(0x99,0x0f);
	Wrt_Reg_3052(0x9a,0x04);
	Wrt_Reg_3052(0x9b,0x05);
	Wrt_Reg_3052(0x9c,0x06);
	Wrt_Reg_3052(0x9d,0x07);
	Wrt_Reg_3052(0x9e,0x0f);
	Wrt_Reg_3052(0x9f,0x0e);
	Wrt_Reg_3052(0xA0,0x00);
	Wrt_Reg_3052(0xA1,0x01);
 
	Wrt_Reg_3052(0xb0,0x0e);
	Wrt_Reg_3052(0xb1,0x0f);
	Wrt_Reg_3052(0xb2,0x0e);
	Wrt_Reg_3052(0xb3,0x0f);
	Wrt_Reg_3052(0xb4,0x07);
	Wrt_Reg_3052(0xb5,0x06);
	Wrt_Reg_3052(0xb6,0x05);
	Wrt_Reg_3052(0xb7,0x04);
	Wrt_Reg_3052(0xb8,0x0f);
	Wrt_Reg_3052(0xb9,0x0f);
	Wrt_Reg_3052(0xbA,0x01);
	Wrt_Reg_3052(0xbB,0x00);
 
	Wrt_Reg_3052(0xc6,0x0e);
	Wrt_Reg_3052(0xc7,0x0f);
	Wrt_Reg_3052(0xc8,0x0e);
	Wrt_Reg_3052(0xc9,0x0f);
	Wrt_Reg_3052(0xca,0x07);
	Wrt_Reg_3052(0xcb,0x06);
	Wrt_Reg_3052(0xcc,0x05);
	Wrt_Reg_3052(0xcd,0x04);
	Wrt_Reg_3052(0xce,0x0f);
	Wrt_Reg_3052(0xcf,0x0f);
	Wrt_Reg_3052(0xd0,0x01);
	Wrt_Reg_3052(0xd1,0x00);
 
 
	Wrt_Reg_3052(0xFF,0x30);
	Wrt_Reg_3052(0xFF,0x52);
	Wrt_Reg_3052(0xFF,0x02);
 
	Wrt_Reg_3052(0x28,0x0B);
	Wrt_Reg_3052(0x29,0x07);
	Wrt_Reg_3052(0x2A,0x81);
 
	Wrt_Reg_3052(0xFF,0x30);
	Wrt_Reg_3052(0xFF,0x52);
	Wrt_Reg_3052(0xFF,0x00);
	Wrt_Reg_3052(0x36,0x01);	//MADCTRL orientation def 2
//	Wrt_Reg_3052(0x3A,0x70);
 
 
	Wrt_Reg_3052(NV3051D_CMD_SLPOUT,0x00);
	HAL_Delay(200);
	Wrt_Reg_3052(NV3051D_CMD_DISPON,0x00);
	HAL_Delay(10);
 
 
  LCD_LIGHT_GPIO_Port->BSRR = LCD_LIGHT_Pin;
 
    return 0;
}

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SkeleSt
Associate II

‎2024-07-16 09:48 PM

Hi MM.1, I'm facing similar issues trying to initialize a NV3052C. Have you had any updates since then on getting your display to work?

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