STM32H573 : RNG Seed Error (SEIS) when used with TZEN=1 and STiRoT

[hicham75]

Hi,

I try to use PKA for some ECDSA computation. For this purpose I needed to use PKA block. However, in SR register, I never get INITOK bit set.

I am working with TrustZone enabled. So, STiRoT is executed before my program.

After investigation, I've seen that bit SEIS in  RNG_SR is set. (while CEIS=0)

Despite reference manual stating in this case, it means some thing went wrong and RNG was able to auto-reset and recover, I think this is what is preventing PKA INITOK to be set.

"INITOK: PKA initialization OK
This bit is asserted when PKA initialization is complete. When RNG is not able to output proper
random numbers INITOK stays at 0."

With same program and with TrustZone disabled(Hence, STiRoT is not executed), RNG is correctly configured without any SEIS error and PKA INITOK bit is set.

I am using RNG in A configuration.

RNG = {
  CR = 0xf00e04,
  SR = 0x41,
  DR = 0x31b4c84e,
  NSCR = 0x3af66,
  HTCR = 0x6a91
}

HCLK(AHB2) is 250 Mhz and HSI48 is used for RNG sampling.

Could someone help with this issue or point any additional configuration to be checked?

Regards

[STea]

Hello @hicham75 ,

I'm able to reproduce the issue that you are mentioning, and I have the same behavior after generating a new project following the Wiki steps with the difference being the activation of RNG and PKA in MX.

A ticket has been submitted for investigation internally ticket number 200855 (for internal reference only)

I'll get back to you as soon as I get more updates about this case.

Regards

[hicham75]

Hi @STea 

Do you have any update on the internal ticket?

Regards,

[CMYL]

Hello @hicham75,

We are still working to understand this behavior. 

In the mean time can you change the RNG_CR configuration to 0x00F10E04 ? It will divide by 2 the RNG kernel clock.

Best regards,

Younes 

[hicham75]

Hi @CMYL 

I've just tried the workaround you suggested but still getting the same issue:
SR showing seed error(0x41) and PKA not able to initialize.

RNG = {
  CR = 0xf10e04,
  SR = 0x41,
  DR = 0xe7d44496,
  NSCR = 0x3af66,
  HTCR = 0x6a91
}

It would be helpful if there is any workaround to proceed even at low performance when waiting for a solution.

Regards,

Hicham.

[CMYL]

Hi,

I suggest to check with: 

RNG_CR= 0x00F10F04
Then increase the RNG clkdiv progressively as follows:

RNG_CR= 0x00F10F04
RNG_CR= 0x00F20F04
RNG_CR= 0x00F30F04
RNG_CR= 0x00F?0F04

Note that the original configuration is working well with PKA when TZ disabled !!

Cordialement

[hicham75]

Hi @CMYL ,

I tested many values (1 through 10 for clock divider), the issue is always there.

Unfortunately, I cannot disable TZ.

Regards,