About STM32H7 SPI CRC length

[Gpeti]

Hello,

I need to enable CRC on my SPI communications. My STM32H7 is the Master and it will send most of the times 4 bytes commands to the Slave. I have chosen DSIZE = 32 bits to speed up the processing, since the copy of data to the FIFO is done by software in polling mode. As far as I understood in this configuration I have to choose a CRC of 32 bits but this means half of the bandwith is used by CRC. If I want to use smaller CRC size, I understood I have to set a smaller DSIZE but then it will increase the software time (4 copy to FIFO instead of one for example with DSIZE = 8 bits).

My question is: did I understand the CRC size constraint correctly ? And what is the explanation to this constraint ?

[Tesla DeLorean]

I would expect you'll need to pick a transfer size that matches the size of the CRC, so you're all dealing in common units of size.

Putting 4 bytes in the FIFO surely isn't that expensive?

The way the CRC is generated and output, isn't exactly cheap either, and requires mode switching and interaction.

If you want to leave and forget, it might actually be cheaper in CPU cycles to just compute the CRC in SW before sending a monolithic packet, using DMA.

[Gpeti]

Well, for me it does not make a lot of sense to have a CRC as long as the data. At the end, with my setup, (send very frequently 4 bytes commands) half of the bandwith is used for CRC so it's surprising.

About your second comment, it's a good idea except it's a pity not to use the HW mechanisms 🙂

[waclawek.jan]

I don't use H7 but IMO if you use DSIZE=8 you still can read/write 4 bytes at once as a full word from/to SPI->DR, see Data packing subchapter of the SPI chapter.

JW

[Gpeti]

Good point. You're right. But now I am wondering the benefit to use DSIZE= 32 ? I will try to do some testing.