Hi.
I init global array DMABuf[33] = {0}; According C++ standard it must be filled zeros.
DMABuf placed into SRAM1(2) i.e. SRAM D2. Immediately after reset the buffer contain zeros. After initialisation DMA, buffer and all SRAM D2 contain random numbers.
Section declaration in ld file:
/* DMA buffer output section */
.bss.dmabuf :
{
. = ALIGN(32);
_sbss.dmabuf = .; /* create a global symbol at start */
*(.bss.dmabuf)
*(.bss.dmabuf*)
. = ALIGN(32);
_ebss.dmabuf = .; /* create a global symbol at end */
} >RAM_DMA
I try to fill SRAM with zeros
uint8_t arrTxADC[lenBufSpiDma] __attribute__((aligned (32))) __attribute__((section(".bss.dmabuf"))) = {0};
uint8_t arrRx_ADC[lenBufSpiDma] __attribute__((aligned (32))) __attribute__((section(".bss.dmabuf"))) = {0};
But compiler (or IDE) not fill this section with zeros when generate starting code (startup_stm32h725igkx.s), so I do this manually at the same manner as IDE code generator make it for .bss section.
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Mannualy zero fill the _sbss.dmabuf segment. */
ldr r2, =_sbss.dmabuf
ldr r4, =_ebss.dmabuf
movs r3, #0
b LoopFillZerobssDMA
FillZerobssDMA:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobssDMA:
cmp r2, r4
bcc FillZerobssDMA
It work good. But just after code in void MX_DMA_Init(void):
/* DMA controller clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
But memory viewer show that all SRAM2 filled with trash (of course my array is filled nonzero values). Stop, Stop, stop! SPI not receive any data, DMA interrupt is not enabled, nothing is done. I think the reason is enabling clock of D2 domain (DMA controller share clock with SRAM2). After enabling clock SRAM2 is filled with garbage.
So it is not problem to write code, that initialize buffer with zeros after enabling all periferia. But I want to understand why SRAM D2 filled with non zero and initialisation (ASM) code fill it with zeros without any problem even with disabled D2 clock (I view it via STLink SWD memory viewer).
Thanks, any suggestion?
