About Aleks

Aleks · 2023-04-13

Hi.Is it possible to reconfigure one or some regions MPU without fully disabling MPU?I need configure for example ITCM memory for RW access when load code and set to RO mode after code copied completed.Code copied from SDRAM to ITCM, so MPU needed fo...

Aleks · 2022-12-11

Hi, dear colleagues!I use OSPI interface to connect MCU with QSPI NAND flash.For some commands (for ex. PAGE READ) of used NAND device there is 0 data bytes and HAL_OSPI_Command_IT() work proper.But some commands (for ex. SET FEATURE) has one (or mor...

Aleks · 2022-04-20

Hi!I use SRAM 1 (0x30000000 - 0x30003FFF) in D2 domain for USART2, USART3 DMA buffers. All work clean. If I use SRAM2 (0x30004000 - 0x30007FFF) just after running debug it's all right. But after "Reset chip and restart debug session" the first access...

Aleks · 2022-04-13

Hi.It seems, that sometimes data in cached memory is corrupted.DMA transfer data from SPI to SRAM2 (0x30000000). I use ping-pong buffer in SRAM2 (two similar buffers). Data processing performing for first part of the buffer in thread, while second it...

Aleks · 2022-04-01

Hi!I try to set IRQ priority to 3 and subpriority to 2.HAL_NVIC_SetPriority(EXTI9_5_IRQn, 3, 2);I suppose that correspond NVIC IPR [23] now is 0x32. But it is 0x30. I read AIRCR PRIGROUP (it is 3).uint32_t PriorityGroup = NVIC_GetPriorityGrouping();A...

Aleks · 2022-05-04

Hi!The same question for STM32H725 (RM0468). But in the reference for STM32F7 this bit is described:Bit 5 BUSY: Busy statusThis bit defines the status of the SDRAM controller after a Command Mode request0: SDRAM Controller is ready to accept a new re...

Aleks · 2022-04-21

Aleks · 2022-04-20

Thank you for article.Some comments:CMSIS library check size and address alignment inside CB_InvalidateDCache_by_Addr(). Align buffers should be done in linker script.Cache invalidate need to be performed before starting DMA receive and after DMA rec...

Aleks · 2022-04-18

Hi Piranha!I read carefully your comments in the topic. I invalidate buffers before start accept data from DMA and after receiving is completed. Problem is seems solved. Yes, even for receive part the invalidation must be done before passing buffers...

Aleks · 2022-04-13

Piranha and TDK thaks a lot!It seems that reason in sequential read and write to buffer by means of my code, i. e. CPU read modify and write data to cachable buffer.I suppose there are possible issues:There is cache eviction when CPU write to buffer,...

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STM32H725 reinit MPU.

HAL_OSPI_Command_IT vs HAL_OSPI_Command, when cmd->DataMode != HAL_OSPI_DATA_NONE

STM32H725 SRAM1 vs SRAM2 in D2 domain

STM32H7 cache and DMA transfer error rate.

STM32H725 NVIC priority and subprioririty

Re: STM32H7 FMC SDSR busy bit is not documented or doesn't exist?

Re: STM32H725 SRAM1 vs SRAM2 in D2 domain

Re: DMA is not working on STM32H7 devices

Re: STM32H7 cache and DMA transfer error rate.

Re: STM32H7 cache and DMA transfer error rate.