Wich is the STM32F429 PLLN maximum frequency?

[TCabr.1]

User' manual says that the maximum PLLN or VCO output frequency should be between 100 and 432 MHz (pg. 227). However, I was trying to set the PLL clock and the SysClock to 180 MHz and also respect the 48 MHz clocks.

One possible solution is to set the PLLM to 4, PLLN to 360, PLLP to 4, and PLLQ to 15. Although, it leads to a VCO output frequency of 720 MHz.

The curiosity was that it worked. USB frequency is at 48 MHz, PLL and SysClock are at 180 MHz. So, my questions are:

1 - What are the problems with the VCO output frequency at 720MHz?

2 - I'm using USB HS, not the FS one. So, should I keep the USB FS clock at 48MHz?

3 - How should I configure PLL to operate at 180 MHz and use the USB HS?

Ps. My PLL clock source is HSE at 8MHz.

[TDK]

1) The max VCO_OUT frequency is 432 MHz per the datasheet. If you go beyond that, maybe it works, maybe not, but it's not guaranteed. Maybe it works at most conditions but will fail at temperature extremes.

2) If you're using USB HS with the internal FS PHY, you need a 48 MHz clock. If you're in HS mode with an external PHY, you don't need this clock (but the external PHY chip will allow you to supply one to it).

3) If you need the 48 MHz clock, you can't. 168 MHz is the best you can do.

[TCabr.1]

First of all, Tanks for your answer.

Secondly, I understand that use should respect what is on the datasheet and the user's manual. But, when I go to the device datasheet, pg 124 - table 43 - Main PLL characteristics, It says that the characteristics are "derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 17".

When I go to Table 17, I notice that Vdd ranges from 1.7 to 3.6V.

Once my application always operates at 3.6V, and as the VCO is a voltage-controlled resonator, I ask myself, "Could I have a VCO_OUT at 720 MHz?"

[Tesla DeLorean]

Well I've certainly worked with courser geometry chips which wouldn't have issues with 600-800 MHz VCO frequencies.

Likely to pull more power in the VCO and divider chains. Seem to recall the F2/F4 wanting something like 2 - 4 MHz for the PLL comparison frequency.

You'd get to test, characterize and qualify what you're comfortable shipping

[Piranha]

There is another way how to look at this. Decreasing the CPU clock from 180 MHz to 168 MHz, you are losing less than 7% of the clock cycles. If such a loss is critical, then the project is doomed anyway. If it's not critical, you can afford losing those few %.

[TCabr.1]

Well, I sure can look this way. But, I'm trying to gain some %. In fact, increasing my PLL frequency by 7% leads to an application improvement of about 32%.

[Piranha]

That's interesting. What is it doing (from a technical standpoint)? Also an "impolite" question - is it using CubeMX/HAL code?

[TCabr.1]

1 - Basically, multiple trigonometry operations and external memory R/W.

2 - Yes and No. Yes, an old STM HAL is indeed in use. No, we're not using the STM IDE.

The fact that increasing PLL clock by X leads to an increase in the application performance of Y (Y > X) can be explained by the dependencies in our software. The mcu core must wait for the peripheral response to continue its tasks... So, we gain in the SYSCLK and in the other PLLs.

[TCabr.1]

After a lot of discussions, readings and tests, we come to the following @TDK​ :

1 - We need a manifestation from ST regarding if we can work at 720 MHz (VCO clock) once our power source always will deliver 3.3V. So, I flagged this post.

2 - Yes, you're right. We're using internal PHY, so the 48 MHz is necessary.

3 - Looking forward to ST's response.

Thanks again.

[Piranha]

So it's because of bus speeds. By the way, if you are at a design stage, consider using F7 - it can be set to the maximum 216 MHz with simultaneously generating 48 MHz for USB from the main PLL. And, apart from the Cortex-M7 core, which is twice as capable, but requires a cache management and proper use of memory barriers at some places, the rest of the MCU is almost the same as F4 with some additional features.