Why is my OC Toggle timer output inconsistent?

[Julian Carneiro]

Posted on July 04, 2018 at 21:03

Using TIM1 Channel 1N and Channel 2N, where Channel 1N is used for PWM output and Channel 2N is used for Toggle output, the Toggle output polarity is inconsistent. I stop both timer channels (HAL_TIMEx_PWMN_Stop and HAL_TIMEx_OCN_Stop), and have a temp uint32_t where I write to the TIM_CCER_CC1NP and TIM_CCER_CC2NP bits in a while loop that does

while(((htim1.Instance->CCER & (TIM_CCER_CC1NP | TIM_CCER_CC2NP)) != tempccer) {

htim1.Instance->CCER &= ~(TIM_CCER_CC1NP); htim1.Instance->CCER &= ~(TIM_CCER_CC2NP); htim1.Instance->CCER |= tempccer; };

so essentially,

while(value is not set) {

set value;};

I have been looking at the registers and, for example, when the CCER has 0x4C written to it (CC2NP = 0, CC2NE = 1, CC1NP = 1, CC1NE = 1) I have cases where the output on the channel before the counter begins toggling can be high or low. All other registers (apart from ones that change dynamically like CNT or PSC) have identical values across all cases and sometimes still it outputs either high or low seemingly randomly. Can someone help me with why this is happening?

Thank you.

[waclawek.jan]

Posted on July 05, 2018 at 10:22

I don't quite understand your post, but generally, in toggle mode, you don't have a defined state of output just by stopping the timer. Switch TIMx_CCMRy.OCzM to some of the 'force' modes (i.e. 0b100 or 0b101) to achieve a defined output state, and then back to toggle.

JW

[Julian Carneiro]

Posted on July 10, 2018 at 21:08

Hi,

Yes I ended up using forced output mode. I believe that stopping the timer just makes it hold its level. Using forced output modes sets it properly then starting toggle mode has worked.

Thank you!