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Why is MPU not generating any fault?

Muzahir Hussain
Associate III
Posted on November 09, 2017 at 14:16

I want to protect a memory region from writing. I've configured MPU, but it is not generating any faults.Please help.

Here are the registers configuration:

MPU_RNR = 0x00000000;   // using region 0

MPU_RBAR = 0x20000000; // base address is 0x20000000

MPU_RASR = 0x0700110B; // Size is 64 bytes, no sub-regions, permission = 7(ro,ro), s=b=c=tex=0

MPU_CTRL = 0x00000001;  // enable MPU

Now when I write in this region of memory, it does not generate any exception and writes successfully.

__asm(

'LDR R0, =0x20000000\n\t'                        // load address in r0, 0x20000000

'MOV R1, 0x77777777\n\t'

'STR R1, [R0,&sharp0]'                                    // write to address 0x200000000

);

This is the definition of handler:

void MemManage_Handler(void)

{

__asm(

'MOV R4, 0x77777777\n\t'

'MOV R5, 0x77777777\n\t'

);

}

I am writing to r4 and r5 just to make sure if the handler was executed or not. This has nothing to do with the rest of the program.

Here's a complete source code:

&sharpdefine MPU_CTRL  (*((volatile unsigned long*) 0xE000ED94))

&sharpdefine MPU_RNR    (*((volatile unsigned long*) 0xE000ED98))

&sharpdefine MPU_RBAR (*((volatile unsigned long*) 0xE000ED9C))

&sharpdefine MPU_RASR (*((volatile unsigned long*) 0xE000EDA0)) 

void Registers_Init(void)

{

   MPU_RNR = 0x00000000;

   MPU_RBAR = 0x20000000;

   MPU_RASR = 0x0700110B;

   MPU_CTRL = 0x00000001;

}

void MemManage_Handler(void)

{

   __asm(

         'MOV R4, 0x77777777\n\t'

         'MOV R5, 0x77777777\n\t'

      );

}

int main(void)

{

   Registers_Init();

   __asm(

      'LDR R0, =0x20000000\n\t'

      'MOV R1, 0x77777777\n\t'

      'STRD R1, [R0,&sharp0]'

      );

   return (1);

}

void SystemInit(void)

{

}

#programming #mpu #keil-uvision #fault-exception #stm32f103rb #memmanage-hard-fault
15 REPLIES 15
David SIORPAES
ST Employee
Posted on November 09, 2017 at 15:48

Is the exception enabled with

SCB->SHCSR = 0x01 << 16;

NVIC_EnableIRQ (MemoryManagement_IRQn);

?

Can you share the full source code ?

Posted on November 09, 2017 at 16:17

>>

Can you share the full source code ?

Or at least the smallest free standing and compiling code that demonstrates/illustrates the issue, and the test case.

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..
Posted on November 09, 2017 at 17:21

Thanks for reply. I've shared the source code.

Posted on November 09, 2017 at 17:25

I've shared the source code. Thank u.

Posted on November 09, 2017 at 18:18

So, seems that the MemManage fault is not enabled and will therefore default to HardFault. See 

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihieffb.html

.

Also,

MemoryManagement_IRQn

seems not to be enabled in the NVIC.
Posted on November 09, 2017 at 18:50

How do I enable MemoryManagement_IRQ in NVIC? I've enabled the 

MemManage fault from 

 System Handler Control and State Register, and it's still not working. So kindly tell me how do I use NVIC?

Posted on November 09, 2017 at 19:04

I've reported this above: you can use CMSIS call

NVIC_EnableIRQ (MemoryManagement_IRQn); 

Posted on November 09, 2017 at 21:17

Thanks. Lastly, is there any problem with my registers configuration?

Posted on November 10, 2017 at 20:42

Nope, everything looks fine.

Double check with the enclosed file which triggers MPU fault on a STM32L

________________

Attachments :

mpu-test.c.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006Hy9y&d=%2Fa%2F0X0000000b5s%2F4P0xnoEeeFavMwdZkfaWSNrx0r5Kt69u4LuDuNPv8K0&asPdf=false