Whether flow control byte is needed in the SPI frame for STM32F407？

[JieShen_Jason]

Hi，

There is a STM32F407 on my board to configure and control the optical module. Also, STM32F407 use SPI to interface with CPU. STM32F407 work as SPI slave mode, and CPU work as master mode. Some protocol require one flow control byte in SPI timing, such as OIF protocol. My understanding is :

For read operation. After slave receive the operation code and address, slave need time to prepare data according to address then put the data into TX_Buffer. This all will be finished in the one clock period as below red mark shown. If slave can't finish the job in time, slave must inform to host through flow control byte .

My question is whether flow control byte is needed in the SPI frame for STM32F407？or it can mitigate this issue through reducing the SCK frequency, not through flow control byte?

Thanks in advance!

Best regards!

Jason

[Andrew Neil]

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@JieShen_Jason wrote:

There is a STM32F407 on my board

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What board is it? Please give details - see: How to write your question to maximize your chances to find a solution

In particular:

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@JieShen_Jason wrote:

optical module.

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What optical module?

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@JieShen_Jason wrote:

STM32F407 use SPI to interface with CPU.

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What CPU?

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@JieShen_Jason wrote:

My question is whether flow control byte is needed in the SPI frame for STM32F407？

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Whether it's needed or not has nothing to do with the STM32.

If the STM32 is communicating with a device which uses it, then the STM32 will have to handle it!

[TDK]

> STM32F407 on my board to configure and control the optical module

So STM32 is master here?

> STM32F407 work as SPI slave mode

???

A flow control byte is not standard in SPI communication. You'll have to work out what you're talking to and whether or not that device needs it. Your architecture doesn't quite make sense.

CPU -> STM32 -> Optical Module

SPI can only have master and slave, not a chain of 3 devices.