Whether flow control byte is needed in the SPI frame for STM32F407？

[JieShen_Jason]

Hi，

There is a STM32F407 on my board to configure and control the optical module. Also, STM32F407 use SPI to interface with CPU. STM32F407 work as SPI slave mode, and CPU work as master mode. Some protocol require one flow control byte in SPI timing, such as OIF protocol. My understanding is :

For read operation. After slave receive the operation code and address, slave need time to prepare data according to address then put the data into TX_Buffer. This all will be finished in the one clock period as below red mark shown. If slave can't finish the job in time, slave must inform to host through flow control byte .

My question is whether flow control byte is needed in the SPI frame for STM32F407？or it can mitigate this issue through reducing the SCK frequency, not through flow control byte?

Thanks in advance!

Best regards!

Jason

[JieShen_Jason]

Hi

Using this  "flow control" mechanism will come with additional software effort. If reducing the frequency of SCK could resolve this issue, I think it will be cost-effective.

Thanks in advance!

Best regards!

Jason

[Ozone]

> If reducing the frequency of SCK could resolve this issue, I think it will be cost-effective.

Not sure what exactly you mean with "frequency of SCK."
I think you mean the SPI clock frequency, and configured in the setup phase- usually somewhere between 1 MHz to 25MHz.

But with SPI, you cannot influence individual clock periods, like e.g. with I2C.
Not only is the MCU bit timing and signal handling under hardware control (i.e. the configuration set before), which means the core only sees completed transfers (bytes).
But more so, the signal timing of the transfer is fully determined by the master, which is the "CPU" in your case.

I think there is no way around a more sophisticated protocol, which includes "flow control".

[JieShen_Jason]

Hi：

get it!

Thanks!

Best regards!

Jason