Where is the interrupt on pin D1 for SDIO handled by the STM32H7?
I asked a question around this issue late last week so I don't want this to appear as a double post but I think this is more specific:
To paraphrase
"The interrupt concept is used to inform the host of changes in the card status using the SDMMC_D1/IRQ pin in 1-bit or in 4-bit data bus mode. SDIO interrupts are sent from the card to the SDMMC host when the card detects an external event. Interrupts are only sent outside the data transfer periods. The SDMMC host detects interrupts sent on the SDMMC_D1 pin once the SDIOEN configuration bit in the data control register is enabled. While the DPSM remains in Idle state and in Busy state between data blocks for DS, HS, SDR12 and SDR25 speed or after the last data block in all speed modes, all low levels on the SDMMC_D1 pin are detected as interrupts from the card to the host."
Assuming that all transfer routines work correctly for upstream/downstream DATA + CMDs for SDIO, using the HAL SDMMC library.
Where (preferably in HAL) does one detect a D1 interrupt sent from Slave device on the STM32?
I do not want to poll (wait for RESET state of pin) outside of transactions as this would be a waste of precious cycles.
Surely there is something in the peripheral that detects this, flags it and allows for other SDIO transfers to occur in tandem?
Thanks again for any help