2025-07-08 11:23 AM
Hello,
I'm working with the STM32H745ZITx and trying to receive data over USART3 using RX DMA. However, the usart_rx_dma_buffer remains all zeros — as if no data is written. Here’s what I’ve checked:
:small_blue_diamond: DMA Configuration:
DMA1_Stream0, Peripheral-to-Memory direction
Tried both Circular and Normal mode
DMA RX request enabled for USART3
HT and TC interrupts are enabled
NVIC settings verified
:small_blue_diamond: Memory & MPU:
RX buffer is aligned using __attribute__((aligned(32)))
Proper cache invalidation is applied using SCB_InvalidateDCache_by_Addr()
Buffer region tested in .ld file using both D1 domain (0x2400xxxx) and D2 domain (0x3004xxxx)
MPU region configured as Normal, Cacheable, Shareable
:small_blue_diamond: What I’ve Tried:
IDLE line interrupt is enabled — still no data
TX DMA works correctly
RX DMA callback triggers, but buffer is untouched
Note: I’ve tested both 0x2400xxxx and 0x3004xxxx address ranges for the RX buffer. Even when HT or TC interrupt is triggered, no actual data appears in the buffer.
Has anyone faced a similar issue on STM32H745 and successfully resolved it?
Thank you,
Kemal
2025-07-08 11:56 AM
If HT and TC get triggered, data was received. It could be that the data is 0, in which case there is no problem. Initialize it to something nonzero to tell.
If non-zero data is coming in, but it shows up as zero when read, this is a caching issue. Show the code you're using when this happens.
2025-07-08 12:39 PM
SCB_CleanDCache_by_Addr(
(uint32_t *)(((uint32_t)lwrb_get_linear_block_read_address(&usart_tx_rb)) & ~(uint32_t)0x1F),
usart_tx_dma_current_len
);
void DMA1_Stream0_IRQHandler(void) {
if (LL_DMA_IsActiveFlag_HT0(DMA1)) {
LL_DMA_ClearFlag_HT0(DMA1);
SCB_InvalidateDCache_by_Addr(
(uint32_t *)(((uint32_t)usart_rx_dma_buffer) & ~0x1F),
sizeof(usart_rx_dma_buffer)
);
usart_rx_check();
}
if (LL_DMA_IsActiveFlag_TC0(DMA1)) {
LL_DMA_ClearFlag_TC0(DMA1);
SCB_InvalidateDCache_by_Addr(
(uint32_t *)(((uint32_t)usart_rx_dma_buffer) & ~0x1F),
sizeof(usart_rx_dma_buffer)
);
usart_rx_check();
}
}
Base Address: 0x30047C00 / 0x2407FC00
Size: 512B
Access Permission: All Access Permitted
Instruction Access: Disable
Shareable: ENABLE
Cacheable: DISABLE
Bufferable: ENABLE