What would cause my MCU to be held in reset?

[HLove]

I have a STM32F756 on my PCB. The microcontroller was responding with no problems, has been programmed and software running on it. It was put to the side for a few days, and when picked up again, the micro has become unresponsive and the SEGGER JLink Programmer is unable to connect to it.

This has happened on 6 boards.

My setup is as follows: MCU running at 1V8. The internal PDR is disabled by pulling the pin low. There is an external reset supervisor controlling the RST pin. SWD is used with a JLink debugger.

On power on, the external reset supervisor keeps the MCU in reset for ~60ms after the 1V8 supply is stable. The reset is then deasserted but the RST pin only reaches 0.4V. This is the same without the supervisor there.

I have found an image for a similar STM micro indicating that there is a NFET that is able to pull the RST pin down, depending on the state of watchdog, POR, BOR etc. However, this isn't detailed in the 756 datasheet. What does the reset circuit look like in the 756? Is it able to drive its own reset line? If so, is there any way I can find out what is causing this to keep itself in reset?

Any help you can give would be much appreciated,

Thanks,

Henry

[Tesla DeLorean]

Check voltage on VDDA pin and on VCAP pins.

If you pull BOOT0 high, and reset, can you access the device then?

[HLove]

Hi,

VDDA is at 1.8V. Both VCAP pins are at 1.13V.

I have tried the BOOT pin pulled high. Unfortunately this doesn't help. I don't think it is running at all given the reset never seems to deassert.

Cheers,

[waclawek.jan]

Double-check all GND (VSS) and VDD (including the analog ones) connections direcly on the pins.

The datasheet appers to be very specific about VBAT in this case - how is that connected in your design?

The external supervisor is not push-pull, is it? You did try manually pulling down NRST?

Can you - at least temporarily - pull PDR_ON high?

JW

[HLove]

Hi,

I'm using the BGA package, so directly probing the pins is not possible! We have had 90+ boards already made without this issue arising, so I'm confident that the connections are correct (manufacuring defects aside, but as they worked a few days ago, I'll be surprised if this has manifested).

VBAT is connected to the main 1.8V supply, so should always be on with the remainder of the chip.

Ah, the reset supervisor is push pull. So whenever the WDG kicks in, I'll be pulling a lot of current through the FETs. It's not unfeasible that this is failing open in this case. If I force a watchdog panic, this does cause the external pin of the STM to come low, so it looks like the FET is on world-side of the circuitry. Looks like the smoking gun...

Thanks very much for your help!