What is the lowest voltage change the STM32F407 ADC can detect? Does it support hardware oversampling?

[Robmar]

So the datasheet says "Min VREF+ Positive reference voltage - 1.8 V (1)(2)(3)", and note 3: VDDA -VREF+ < 1.2 V, so with VDDA at 2.925v, VREF of 1.755V would be permitted? Its a bit confusing to me at this point!

Given the ADC 12 bit resolution, the LSB is 439uV, which is too high for my application.

I can use hardware oversampling to increase the resolution, but can't find anything in the 32F407 datasheet about this feature or even an application note so not sure its supported?

[LCE]

Not really, if you got time, maybe lots of oversampling...

But that's a voltage range you usually take external circuits for.

If not an external ADC, then at least an (programmable) amplifier.

[Robmar]

Not sure if oversampling can improve the resolution much more than a bit, but that's worth a try. It will improve accuracy and noise, but its mainly limited to the 1/4096 of VREF+

[MasterT]

I see it other-way, having VREF+ Positive reference voltage - 1.8 (1)(2)(3) MIN, and < 1.2 means you can't apply Vdda > 1.8 + 1.2 = 3 V if REF at minimum 1.8. For 3.3V Vdda , 3.3 - 1.2 = 2.1V REF possible as a minimum value.

https://www.st.com/en/microcontrollers-microprocessors/stm32f407-417.html#documentation

I don't see any sign that F4 adc has hardware oversampling capability, G4 for example, has this feature and description in the Reference Manual.

https://www.st.com/en/microcontrollers-microprocessors/stm32f407-417.html#documentation

Same time, nothing can stop you to do it in software, configure ADC with DMA and summ up all data than right shift. 256 array size allows 4-bits more, so overall resolution 'd reach 16-bits. W/O DMA, using only interrupts for each sample sampling rate would be low, depends on CPU clock, probably less than 0.5 MSPS

[Robmar]

Yes but note 3 is pretty clear no? My VDDA is​ 2.925 so applying note 3., VREF+ max at 1.75 is in limit, or did I miss something?

​Looks like you're right about h/w oversampling, I'll up the buffer size by four then add and shift but I can't take it higher than 13 bits or the b/w will be too low. Need 192khz final b/w at least, ideally 384k. Have to sample to ADC inputs synchronised at maximum rate, so ADC1 and 2, can they by synced or if I start them together they're off the same click so might be okay...

[MasterT]

Vref can't be lower than 1.8V. So, if Vdda 2.925 , Ref can be set to 1.8V, for any value Vdda like, 2.5V, 2.0V, 1.8V etc, minimum Vref is still 1.8V.

[Robmar]

So note 3 is totally wrong then? Surely if VDDA is lower VREF min drops too​, or is there a reason it must be no lower than 1.8v, any reference document beyond the datasheet?

The datasheet vref minimum spec of 1.8v perhaps isn't a fixed min voltage over gnd, but the lower limit below VDDA​, a difference voltage. Be good if an STM engineer might confirm.

[MasterT]

I'd ignore note 2 as non sense . Obviously, if Vdda max 3.6V and Vref min 1.8V, than note 2 is always true. I checked with F446re DS, see:

[Robmar]

That's the same formula as the f407vg, so putting in my figures 2.92 - 1.75 = 1.17, therefore < 1.2

​But the notes as you say make it unclear.

So you think vref must be > 1.8 over grnd, vss?​

[Piranha]

> So you think vref must be > 1.8 over grnd, vss?​

From the same datasheet:

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

> I don't see any sign that F4 adc has hardware oversampling capability

One can do it in software also.