What are the missing Port F and G pins used for in Nucleo STM32H7A3ZI?

[JChan.0]

I'm trying to determine how easily it is to switch between Nucleo controllers in the F4, F7 and H7 series, for future adaptations of a project.

I noticed for a few Nucleo boards (single-core H7A3ZI, also dual-core ones H745ZI and H755ZI), there are a number of pins in Port F and Port G that are not accessible at all through the Morpho (CN11/CN12) and Zio connectors, nor on CubeMX.

Does any one know why, and what they are used for? I know the H7A3ZI has the highest SRAM. Are those pins used to improve the SRAM or for something else? I noticed most of the missing Port F and Port G pins have an FMC alternate function.

[TDK]

> a number of pins in Port F and Port G

Which pins are you asking about in particular?

[Andreas Bolsch]

The schematics are available on ST's website, the details are inside ... Some are used for Ethernet interface (despite the fact h7a/b don't implement that).

[JChan.0]

PF0, PF1, PF2, PF3, PF4, PF5, PF12, PF13

PG0, PG1, PG2, PG3, PG4, PG5, PG15

[JChan.0]

Thanks for the suggestion. That actually didn't occur to me. I just checked, but unfortunately they were not listed there either. I might try to dig around the manufacturing files.

[TDK]

> STM32H7A3ZI

> PF0, PF1, PF2, PF3, PF4, PF5, PF12, PF13

> Does any one know why

Those pins don't exists on the microcontroller chip itself. A package can only fit so many pins, and the ones that don't fit are left out. Since they're not on the chip, they wouldn't be on any of the connectors on the board either.

> what they are used for?

The datasheet lists all possible functions for all pins. Here they are for port F: