What actions are required on DMA complete?

[DOCon.1]

Hi - I'm learning DMA, and am having some trouble. (L4, but this applies to most/all STM32s)

For SPI, the RM States this:

"To close communication it is mandatory to follow these steps in order:

1. Disable DMA streams for Tx and Rx in the DMA registers, if the streams are used.

2. Disable the SPI by following the SPI disable procedure.

3. Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the // SPI_CR2 register, if DMA Tx and/or DMA Rx are used."

For other peripherals, no stop procedure is mentioned.

Do I really need to disable SPI? Are the other steps mandatory as well? (Not listed here, but I believe a mandatory step would also be clear the interrupt flag, if using an ISR)

RM: "The DMA channel must be disabled in order to reload a new number of data items into the DMA_CNDTRx register."

Specifically: Do I need to disable the appropriate `TXDMAEN` and `RXDMAEN`? These are included on most DMA-supporting periphs. The quote above implies I must disable the channel in the DMA CCRx reg. (I believe this is step 1 in the SPI instructions. Note that I'm using L4, which calls them "channels", so perhaps this was copy+pasted from a diff RM?) If using SPI, should I pull CS high in the ISR?

Tangent: What happens if the device enters `stop` mode while a DMA transfer is running? Thank you.

[waclawek.jan]

Obviously copy/paste from a device with dual-port DMA (where "channels" are indeed called "streams"), maybe 'F7 which precedes 'L4 in the timeline https://community.st.com/sfc/servlet.shepherd/version/renditionDownload?rendition=ORIGINAL_Png&versionId=0680X000006qOEu&operationContext=CHATTER&contentId=05T0X00000NPLil

That procedure may be needed to avoid some nasty gotcha, e.g. a potentially hanging latch in the DMA trigger path, if you abort SPI amidst receiving a frame.

> What happens if the device enters `stop` mode while a DMA transfer is running?

You mean, one of the 3 stop modes (or how many your model you did not disclose has - I look at the 'L476 now)? Well, nothing, it simply stops amidst the transfer as it loses clocks. I'd expect all bus transfers to finish cleanly upon stop; okay this is not documented AFAIK but would be nasty if it would not be the case(*). As all 3 stop modes promise to preserve registers content, it will probably resume when the clocks resume after wakeup.

I am not ST, though.

JW

(*) it sort-of is, for Stop0 and Stop2 the RM says "If an access to the APB domain is ongoing, The Stop 2 mode entry is delayed until the APB access is finished."