Want to store data in SRAM D2 domain, what is missing to avoid Hard fault?

[Joerg Wagner]

Instead of using DTCMRAM or SRAM D1 domain via AXI, I set up the linker file to use D2.

In system_stm32h7xx.c I added the lines:

  /* Change the switch matrix read issuing capability to 1 for the AXI D2 target (Target 2 and INI2) */
  *((__IO uint32_t*)0x51003108) = 0x00000001;
  *((__IO uint32_t*)0x51043108) = 0x00000001;

But executing

/* Call static constructors */
    bl __libc_init_array

in startup_stm32h743xx.s a Hard Fault is thrown.

What is missing to have normal data stored in D2 domain?

Thank you for any tipps.

[HaiHuynh08]

It is in Table "AXI interconnect register map and reset values", Reference Manual. This table shows Offset of AXI_TARG2_FN_MOD (0x3108) and AXI_INI2_FN_MOD (0x43108). Because the base address of Global Programmer View (GPV) is 0x51000000 (as Table "Register boundary addresses"), so:

• AXI_TARG2_FN_MOD at 0x51003108
• AXI_INI2_FN_MOD at 0x51043108