VREF+ exceeding VDDA during power on/off

[stevedebonis]

I'm trying to understand the following excerpts from the STM32L476 datasheet, which seem to contradict:

In Table 20 - the absolute maximum voltage on the VREF+ pin is given as 4.0V (VREF+ I assume falls under the "other" category).

Table 76 seems to indicate that VREF+ can never exceed VDDA. Does this include during power on and power off, or is this just a steady-state condition to satisfy the accuracy performance of the ADC? And if the latter, is it fair to assume that VREF+ can be as high as 4V, even if VDDA is 0V, as Table 20 would suggest?

[STOne-32 · Accepted solution]

Dear @stevedebonis ,

Welcome in our STCommunity and choosing STM32L4 series ! Hope you will enjoy and share with our members valuable knowledge.

Let me clarify what means Table 20 : AMR - Absolute Maximum Rating . It impacts the device reliability and most important permanent damage if the characteristics inside are not met and exceeded even a short exposure. 

Now, regarding the particular question Yes you can have VREF+ up to 4 Volts , but also as show in that last row of the same table  VREF+ can not exceed 0,4 Volts above VDDA even during power up and power down.

 Hope it helps you .

Ciao

STOne-32

[ONadr.1]

If it can happen that Vref remains for some time after/before VDDA is turned off/on, it is advisable to use a resistor connected between Vref source and Vref pin and Vref pin connect with a schotky diode to VDDA (anode to Vref pin). Rezistor value depends on Vref source limit current.

[stevedebonis]

Thank you for the prompt response. I had been looking at rev 8 of the datasheet, which does not include the last line in Table 20. This answers my question.

[stevedebonis]

I'm revisiting this, and may end up using your suggestion. I assume there is a clamping diode internal to the microcontroller that should drive the size of the resistor. Do you know what the current limit for this is?