Vdd being held at 0.7V with backup battery fitted

[paulyoung9]

Posted on March 08, 2012 at 14:07

Hi,

When I switch off the power to my STM32F417 with a backup battery connected, the Vdd rail doesn't drop below 0.7V and Vbat falls rapidly. It looks like Vbat is connected to Vdd and is powering the rest of the circuit. If I briefly short Vdd to ground, it seems to sort itself out. I tried adding a resistor to load up the Vdd rail to see if this would help, but I just got lower voltage (~0.4V) and faster discharge of the backup battery. Seems like it needs a fairly hard short to ground to make it switch off. Has anyone got the battery backup working on STM32F4? Do I need to do some configuration in software before this will work correctly? Thanks. #battery-backup-rtc #inmates-running-asylum #battery-backup #stm32f4 #vbat-stm32f4 #vbat-battery-backup #vbat-stm32f4 #0.7v-rtc-vbat-battery-backup

[waclawek.jan]

Posted on September 10, 2013 at 13:20

There shouldn't be an issue with the 'Z' revision of STM32F4xx in LQFP100, as the PDR_ON pad on the chip is internally connected to VSS. I have a couple of boards here with these devices, battery fitted, experiencing no such problems.

Can you please describe your application - what is your power supply, how fast is it powering down, what is connected on PC13-PC15, do you have any external reset circuitry connected...? JW

[John F.]

Posted on September 10, 2013 at 17:22

Jan,

You wrote, ''PDR_ON ... is internally connected to VSS.'' STM32F407 Data Sheet says, ''On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On all other packages, the power supply supervisor is always enabled.'' Did you mean VDD?

[waclawek.jan]

Posted on September 10, 2013 at 22:22

> Did you mean VDD?

Of course... Sorry... Oh how stupid I am... Thanks for pointing it out 😉 Jan

[digital_dreamer]

Posted on September 12, 2013 at 03:26

Thanks, Jan. That's encouraging news!

The project I'm working on is a printing press counter with waste management features. It drives a 320x240 LCD via SSD1289 controller with FSMC.Currently, I'm using a little Waveshare Core407V development board. Power is via USB with a AMS1117 3.3v linear reg. There's only a 10uF cap on the power rail, but I plan on using a all-in-one SMPS (RECOM Powerline converter), with a 330uF or larger on the final board to squeeze by any brownouts. (The BOR is currently set to level 1 - 2.10-2.40 volts.)With only 10uF, it's powering down extremely fast when I pull the USB cable. However, it still has time to initiate a PVD interrupt (set at 2.8v) and backup 24 bytes with a marker to the RTC backup domain.I have since disabled this feature, thinking that it was the culprit in the RTC battery switching issue. I now backup any time data is modified. However, this change has not made any difference in the switching issue.Nothing is on PC13. The 32.768 KHz crystal is on PC14-15, of course, with 6pF loading caps.A standard 0.1uF cap to VSS is on NRST.I originally had pin 99 (formerly PDR_ON) floating, but is now tied down to VSS.best of wishes,

MAJ

EDIT: I'm getting reports from the field that a counter I had installed a week ago with a 2200uF cap on the output and much, much smaller battery has not displayed any low battery warnings (not confirmed, however). So, it appears that a slower power down setup allows for the proper switching. I need to do some tests...EDIT:Some initial testing: With just hooking up the battery to VBAT with the board off, the current draw is immediately at 45mA. The battery had already drained down to 1.2v at this time.I'm going to check the other board in the field and see what the status is. It may be just the board I'm currently using.MAJEDIT: Man, this forum software is the worst I've used!

[pavel]

Posted on October 20, 2015 at 21:02 Hello Clive, could you please help me with my question about backup SRAM in STM32F427? I have design, where I am using voltage regulator for VDD and VDDA - 3V0. As backup batery I use batery 3.2V connected to VBAT pin6.   My question is, when I save something data to backup registers, and processor will be without main battery, only backup baterry will be connect to VBAT pin, during long time this backup battery will be fall down. Do you know on which woltage minimum, will be this data in SRAM backup registers lost? When VBAT falls below 1,65V data will be lost? or when falls below 1,65V ? because I try to set VBAT voltabe below 1,65V and data stored in SRAM backup register will not be losted/cleared. Data I have stored in

RTC_BKP_DR0, and when Vbat fall below 1,65V, the data was still in this register. I thinking that underthis voltage, will be data from backup SRAM cleared? Is it my assumption corert, or not?

[Tesla DeLorean]

Posted on October 20, 2015 at 22:16

For unrelated questions please start a new thread, not dig up an old one you found via Google. Thanks.

The specification means below 1.65V the behaviour is undefined. What actually happens depends on the specific device, and the temperature. I suspect it would keep content below 1.65V, but that's something you'd have to qualify for yourself.If you want parameters permanently remembered consider FLASH or OTP for long term storage.I don't work for ST, for specific advice in this regard you'll want to speak to your local ST rep or FAE.