Hi all,
I'm planning to use an STM32F405 and its FSMC to interface with an external, parallel 16-bit NOR flash chip from Infineon/Cypress.
This chip has a read page size of 32 bytes / 16 half-words.
When reading a half-word that is located in a page which is currently not in the read "buffer", it takes around 100 nanoseconds to obtain a valid data output, since the chip logic has to fetch the complete page in its buffer first.
When reading values that are in the same page that was already loaded (e.g. the half-word following the one that we read first), the access latency is therefore reduced to around 25 nanoseconds, because the page where it's located is already "cached".
I haven't seen a way to exploit this kind of latency feature in the FSMC NOR flash timing registers.
Do I have to settle with just using the longer latency for every access ? Or is there a way the FSMC can adapt its number of wait state cycles depending on the access ?
Thanks in advance.
