Using DMA in Circular mode does not update the data array

[angeletti2]

Posted on July 25, 2016 at 16:41

Hi guys,

I'm working on STM32F746-Discovery and I'm trying to read through DMA the digital microphone. I would like to save in a circular buffer the readed data, so that I can process it using DSP. The code is pretty simple and I started from the Audio Record and Playback application provided by ST. Firstly I define the buffer array of size 4096

uint16_t audioBuffer[AUDIO_BUFFER_SIZE];

Then inside the ''main function'' I start the recording process

BSP_AUDIO_IN_Init(INPUT_DEVICE_DIGITAL_MICROPHONE_2, 100, DEFAULT_AUDIO_IN_FREQ);
BSP_AUDIO_IN_Record(&audioBuffer[0], AUDIO_BUFFER_SIZE);

Then I'm just checking the array everytime the DMA transfer finish callback is called

void
BSP_AUDIO_IN_TransferComplete_CallBack(
void
)
{
uint32_t index;
for
(index=1000;index<1020;index++)
printf
(
''%d ''
, audioBuffer[index]);
printf
(
''\r\n''
);
}

I obtain the same sequence outputted every half second more or less (maybe a quarter of second). Why the array is not updated? The rest of the code is exactly the same from the demo application. Thanks in advance #cache-coherence #adc #dma #discovery #stm32f7 #board #cache

[Tesla DeLorean]

Posted on July 25, 2016 at 17:22

Make sure you use uncached memory, there is not coherency management here.

[angeletti2]

Posted on July 25, 2016 at 17:59

Thanks clive1, I solved removing the caching. In the case that I want to leave the cache enabled, how can I do it without messing with the buffer?

[yzhang1985]

Posted on July 26, 2016 at 09:25

As clive said, there is no cache coherence between the peripherals (DMA in your case)  and CPU. You'll have to manually program coherence.

Example: before DMAing from memory, call SCB_CleanDCache_by_Addr() to flush the buffer to RAM. Likewise, after DMAing to memory (i.e. in BSP_AUDIO_IN_TransferComplete_CallBack()), call SCB_InvalidateDCache_by_Addr().See AN4839: Level 1 cache on STM32F7 SeriesUnless you're a hardcore optimizer, I doubt you want to do this. I'm an optimization freak, but I'd rather use the dTCM if I want high bandwidth (64bit vs 32bit for regular SRAM), low latency memory.I did some rough latency benchmarks by timing 16 back to back loads using the DWT cycle counter:SRAM: 8.6 cycles/loaddTCM: 2.3 cycles/loaddCache: 1.5 cycles/loadFeel a little misled because the documentation says the dTCM has 0 cycle latency.

[Konstantin Sachkov]

Posted on October 17, 2017 at 19:58

Thank you very much!!!! I've spent 5 days resolving the same problem.

[Tesla DeLorean]

Posted on October 17, 2017 at 20:21

I haven't dug too deeply into the architecture used here, but with other cached ARM platforms there are usually two views of the same memory, you should access things touched via DMA via the uncached view.