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Use Analog Watchdog (ADC AWD) as a reset for timer.

MPian.1
Associate II

I've to count till 30ms, but i've to restart the count if a signal goes above a threshold. So i want to use analog watchdog as trigger source for the timer.

I set up the timer in "slave reset mode" and with "ETR1 through ADC" as Trigger Source. I've also set ETR remap capabilities for TIM! in the correct way. The problem is that the timer never reset so it count to 30 ms every time. Anyone have any advice?

Thanks,

Marco

1 ACCEPTED SOLUTION

Accepted Solutions
MPian.1
Associate II

I find the problem. ADC1_AWD1_OUT stays high so it trigger the reset of the timer only when it goes from 0 to 1. In my application the signal is stable outside the ADW window and i wrongly assumed that this situation will have caused a continuos reset on the timer unless there is a voltage drop outside the window.

Thanks for the help,

M

View solution in original post

5 REPLIES 5

Which STM32?

How is ADC running? Observing it's registers, does it set the watchdog flags as expected?

> I've also set ETR remap capabilities for TIM! in the correct way.

Have you verified this by reading out and checking the TIM registers content?

JW

MPian.1
Associate II

Hi,

Thanks for the reply.

i work with a STM32WB50.

ADC is running ok, AWD1 interrupt flag is set to 1 when the signal is outside the window and to 0 otherwhise.

ADC1_AWD1_OUT is the signal that trigger the timer, but i don't know where to check its value.

The TIM register seems okay

M

> The TIM register seems okay

Show.

JW

MPian.1
Associate II

I find the problem. ADC1_AWD1_OUT stays high so it trigger the reset of the timer only when it goes from 0 to 1. In my application the signal is stable outside the ADW window and i wrongly assumed that this situation will have caused a continuos reset on the timer unless there is a voltage drop outside the window.

Thanks for the help,

M

Good catch.

Thank you for coming back with the solution. Please select your post as Best so that the thread is marked as solved.

JW