2014-09-28 11:37 AM
I've been trying to get my st discovery board to receive data from my computer over the USB. My source is attached. I've been working on this for a long time. The progress is slow. I spent weeks just to figure out that OTG_FS_GCCFG needs to have PWRDWN bit set. The reference manual is little help. It actually doesn't talk about PWRDWN anywhere except to say that it exists.
Both the computer and the board acknowledge they are attached now. The board sees the reset command from the computer. I can see from Microsoft Message Analyzer that the computer tries to send over a GET_DESCRIPTOR into endpoint 0, but It never registers on the board. I never get the expected RXFLVL, or OEPINT interrupt. The OTG_FS_DOEPTSIZ0 should also decrement and indicate that a setup packet has been received, but that never happens. In fact, I get the USBreset interrupt, then the enumeration done interrupt, then everything just goes into suspend state after a few seconds. I suspect the EPENA bit should self clear at some point in OTG_FS_DOEPTSIZ0 but that never happens. I suspect the RxFIFO has problems. The OTG_FS_GRXSTSR and OTG_FS_GRXSTSP and the actual FIFO itself all have the same non-sense value. The value isn't always the same. Right now its 0xFBF3DFFF. The manual says everything should be 0x0 before anything significant happens. In my code I've tried to flush the RxFIFOs but nothing much changes. I've followed the procedures given in the reference manual, but I cant get any indication that the GET_DESCRIPTOR packet has arrived. Can you explain where I went wrong? Is there a better reference regarding how the OTG_FS is supposed to behave and be setup? the source and binary are attached2014-09-30 08:17 AM
Hi robison.don.001,
It seems that the device is not detected by the Host. Are you sure that the Pull-up is enabled: SDIS bit in the device control register (OTG_FS_DCTL) ?To have more insight into the USB libraries using the STM32Cube library please check the USB_Device applications within thehttp://www.st.com/web/en/catalog/tools/PF259243#
package.You can refer also to the following document:http://www.st.com/st-web-ui/static/active/en/resource/technical/document/user_manual/DM00108129.pdf
Regards,Heisenberg.2014-09-30 12:28 PM
Thanks for the hint Heisenberg. I don't know what the soft disconnect bit is. I assume it's the reset value of 0b0, since I never write anything to that register. I'll investigate that when I get the chance. I assume it should be 0b0.
I noticed my PLLN is only 24, the lower limit is ambiguous since the reference manual says HSE*PLLN > 64 and later PLLN > 64 could that be it?2014-10-01 12:57 PM
My problem was the PLL. In the reference manual there is some ambiguity regarding the limits of PLLN. At one point its saying the frequency must be higher than 192, then later it's saying the multiplier itself must be above 192.
I saw an example from ST that gave the entire clock setup portion. It showed their multiplier was 336, while mine was 24. I changed mine to 336 and now the RxFIFO makes sense, the setup packet count decrements, and the RxFIFO interrupt is asserted, so things are much different from this little change.2014-10-08 01:30 AM
OK, great! Do, click ''Mark as helpful post '', if any of my replies helps solve your problem.
Cheers,Heisenberg.