Unable to activate LWIP on STM32H757IIT6

[Pavel_Safar]

I am not able to activate LWIP middleware for M7 core on any dualcore STM32. (I am able to do it on single-core devices and  already have LWIP working on H743 Nucleo)

Steps I have done (exactly in this order):
- create a new project for STM32H757IITx in CubeIDE
- agree usage of default configuration of speculation processing
- enable SYS -> Cortex_M7 -> I cache
- enable SYS -> Cortex_M7 -> D cache
- enable ETH and configure it for M7 core with RMII
- enable FreeRTOS_M7
- enable LWIP for Cortex M7 in the sidebar. 

Now I can see the second bar for LWIP. Runtime context M7 is checked but it is not possible to check "enable" checkbox to activate LWIP. When I put the mouse on the enable checkbox, I can see a warning that "D-cache must be enabled on M7 to use LWIP". But the problem is that D-cache is already enabled. It seems to me like a bug in IDE because I am able to activate it on singlecore devices with the exactly same steps. It also works on M4 core on dualcore H757. 

I found partial workaround using working example from ST member and manually editing IOC file to fit H757 LQFP instead of H747 BGA but this is not a nice solution and it sometimes create problems when regenerating code.

Thank you

[STTwo-32 · Accepted solution]

Hello @Pavel_Safar and welcome to the ST Community :smiling_face_with_smiling_eyes:.

Thank you for reporting this issue. I confirm this bug and i've report it to the concerned team for correction on the next releases (under internal ticket number 178614).

Best Regards.

STTwo-32 

[Pavel_Safar]

Thank you. This is not something that you want to hear when you are working on a thesis and time is running out. :) But that is life. Thank you for your reply - at least I will not waste more time on solving this. If any (temporary) workaround is available, please let me know. 

[Peter3718]

i still run into such issue now with cubeMX6.11.1, is this bug fixed?

Peter