2023-04-27 08:59 AM
I am currently implementing a UART communication on a STM32F1. As I understand from the manual, the ORE bit does block all further Rx until it is cleared but the other error flags (PE, NE, FE) do not block Rx when set.
How is the behaviour of the UART error flags and the data register (DR) in the following 2 scenarios. (in both scenarios 2 bytes are received before checking the SR and DR).
Scenario 1:
** First byte contains an PE/NE/FE error
** Second byte contains a correct byte
If I understood the manual correctly, all error flags (PE,NE,FE,ORE) are now set and DR contains the first (corrupt) byte. Is that correct?
Scenario 2:
** First byte contains a correct byte
** Second byte contains a PE/NE/FE error
My assumption is that the first byte is stored in DR but PE/NE/FE flags are set (because of the second, corrupt byte) and also the ORE. Is that correct?
If both of my assumptions are correct, is it therefore true, that, if 2 bytes are received and all error flags are set, you cannot decide whether the byte in DR is the corrupt one or the correct one?
Thank you,
Markus
Solved! Go to Solution.
2023-04-27 11:55 PM
H @Markus8494
If you receive 2 bytes, I think first one will be available in DR register, and will remain until it is read. 2nd byte will be available in DR only after first one has been read.
Error flags are loaded in SR in line with data present in DR.
So back on your scenarios,
Scenario 1 is correct : Error flags will be present in SR at the time Byte 1 is available in DR. Bye 2 is not available until Byte 1 is read.
Scenario 2 : PE/FE/NE error flags will be set in SR, only after Byte 1 has been read, i.e. when Byte 2 is available in DR.
To address your last question, when data is received (RXNE is raised to 1), flags refers to data present in DR (byte 1 for the first time) :
Regards
2023-04-27 11:55 PM
H @Markus8494
If you receive 2 bytes, I think first one will be available in DR register, and will remain until it is read. 2nd byte will be available in DR only after first one has been read.
Error flags are loaded in SR in line with data present in DR.
So back on your scenarios,
Scenario 1 is correct : Error flags will be present in SR at the time Byte 1 is available in DR. Bye 2 is not available until Byte 1 is read.
Scenario 2 : PE/FE/NE error flags will be set in SR, only after Byte 1 has been read, i.e. when Byte 2 is available in DR.
To address your last question, when data is received (RXNE is raised to 1), flags refers to data present in DR (byte 1 for the first time) :
Regards
2023-05-08 07:51 AM
thanks for the quick response.