Trigger ADC1 scan using TIM1 CC1 on F410RB

[massimiliano2399]

Posted on September 20, 2016 at 13:08

Hi,

I use STM32F410RB, and I need to trigger an ADC1 scan regular conversion every TIM1 CC1 event. I am sure that TIM1 works, because I have an interrupt that is triggered every CC1 event. I tried to configure ADC as follows:

ADC_ChannelConfTypeDef sConfig;


/* ADC Initialization */

AdcHandle.Instance = ADC1;


AdcHandle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;

AdcHandle.Init.Resolution = ADC_RESOLUTION_12B;

AdcHandle.Init.ScanConvMode = ENABLE;

AdcHandle.Init.ContinuousConvMode = DISABLE;

AdcHandle.Init.DiscontinuousConvMode = DISABLE;

AdcHandle.Init.NbrOfDiscConversion = 0;

AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;

AdcHandle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1;

AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT;

AdcHandle.Init.NbrOfConversion = 2;

AdcHandle.Init.DMAContinuousRequests = DISABLE;

AdcHandle.Init.EOCSelection = ADC_EOC_SINGLE_CONV;


HAL_ADC_Init(&AdcHandle);


/* Configure ADC3 regular channel */

sConfig.Channel = ADC_CHANNEL_0;

sConfig.Rank = 1;

sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;

sConfig.Offset = 0;


HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);


/* Configure ADC3 regular channel */

sConfig.Channel = ADC_CHANNEL_1;

sConfig.Rank = 2;

sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;

sConfig.Offset = 0;


HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);


HAL_ADC_Start_IT(&AdcHandle);

But ADC no interrupt is triggered. Which register, which bit are involved in the configuration? best regards Max #adc #timer #stm32f410rb Note: this post was migrated and contained many threaded conversations, some content may be missing.

[Dana Myers]

Posted on November 08, 2017 at 20:44

Experimenting may be fun, but the primary source of information is (ought to be) the RM/DS.

If only Cube and the RM/DS came from the same universe. Of course I refer to the RM/DS in attempting to understand what Cube has emitted. It's always an adventure (on the other hand, it's easier than trying to use MSP430 peripherals, but I digress).

So you wanted to use one of the PWM modes. I don't know how are they called in the Cube parlance.

That's what I thought. I tried 'Active on match' thinking that sounded like a reasonable suspect. Didn't work. Now I'm thinking perhaps I need to reverse engineer the documentation further to figure out what other output mode configuration is required. If only there was a relevant ST example - like, say, the test code they used to qualify this functionality in test. But I fantasize.

Toggle is fine too if it fits other purposes that timer may be used for.

Toggle rather annoys me; it's a hack. It works - and isn't the ISR-based workaround described elsewhere - but it's clearly a hack.

Perhaps I can spend another hour or two and figure out what ST's documentation is trying to tell me, or what it neglects to mention.

Cheers.

[waclawek.jan]

Posted on November 08, 2017 at 20:56

[STM32Cube_FW_F4_V1.15.0]\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h :

/** @defgroup TIM_Output_Compare_and_PWM_modes  TIM Output Compare and PWM modes

  * @{  */&sharpdefine TIM_OCMODE_TIMING                   0x00000000U&sharpdefine TIM_OCMODE_ACTIVE                   (TIM_CCMR1_OC1M_0)&sharpdefine TIM_OCMODE_INACTIVE                 (TIM_CCMR1_OC1M_1)&sharpdefine TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)&sharpdefine TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)&sharpdefine TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M)&sharpdefine TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)&sharpdefine TIM_OCMODE_FORCED_INACTIVE          (TIM_CCMR1_OC1M_2)

So you want TIM_OCMODE_PWM1 instead of TIM_OCMODE_TIMING .

This is the reason why I find 'libraries' superfluous. I wouldn't touch Cube with a stick. YMMV.

JW

[Dana Myers]

Posted on November 08, 2017 at 21:08

So you want TIM_OCMODE_PWM1 instead of TIM_OCMODE_TIMING .

Thanks. Why is this different than TIM_OCMODE_ACTIVE in terms of triggering the ADC? I'd expect one TIM1-clock width pulse at OC1REF with TIM_OCMODE_ACTIVE as long as the CCR register value is inside the up-count range of TIM1.