2021-03-19 07:17 AM
2021-03-19 08:00 AM
SRAM1 and SRAM2 form a continuous area of 128kB. You can use the whole 128kB without any restrictions.
The reason why they are split is, that they can be accessed concurrently by different busmasters (e.g. processor and DMA), see Embedded SRAM chapter in RM0390. This can bring somewhat increased performance in some marginal cases, but is otherwise unimportant.
JW
2021-03-19 08:00 AM
SRAM1 and SRAM2 form a continuous area of 128kB. You can use the whole 128kB without any restrictions.
The reason why they are split is, that they can be accessed concurrently by different busmasters (e.g. processor and DMA), see Embedded SRAM chapter in RM0390. This can bring somewhat increased performance in some marginal cases, but is otherwise unimportant.
JW
2021-03-19 08:06 AM
Great, thanks for the very quick response