The difference between Macronix mode and Macronix RAM mode in OCTOSPI Memory type configurations

[guyan]

I want to use MX25UM51345G on STM32L5. When configuring the Memory type, I found these two mode:

001: Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in

single-, dual-, quad- and octal-SPI modes.

011: Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command

protocol in single-, dual-, quad- and octal-SPI modes with dedicated address mapping.

But I didn;'t found any detials about the difference between these two mode. So what is "dedicated address mapping" means? Is there any example about how to use these two mode? What kind of memory should use Macronix RAM mode?

[ChahinezC · Accepted solution]

Hello @guyan​,

For the dedicated address mapping it refers to the fact that Macronix RAM memory is different from the Macronix memory type as the memory is built differently at the address level, in row and columns.

Regards,

Chahinez.

[Tesla DeLorean]

An App Note or Knowledge Base article about the signalling / protocol level nuances might be helpful, especially if the OCTOSPI is being connecting to an FPGA as a means to read and/or write to some other device/hardware via a fast interface.

I'm thinking burst or FIFO memory, where there's going to be a disparity in rates, ie where the data might get generated at a high rate in synchronous fashion, but can be captured/processed in a burst / packet transfer.